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AT45DB321D-MU Datasheet(PDF) 2 Page - List of Unclassifed Manufacturers |
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AT45DB321D-MU Datasheet(HTML) 2 Page - List of Unclassifed Manufacturers |
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2 / 52 page  2 AT45DB321D [DATASHEET] 3597T–DFLASH–11/2013 1. Description The AT45DB321D is a 2.5V or 2.7V, serial interface, sequential access flash memory ideally suited for a wide variety of digital voice-, image-, program code-, and data-storage applications. The AT45DB321D supports the RapidS serial interface for applications requiring very high speed operations. The RapidS serial interface is SPI compatible for frequencies up to 66MHz. The 34,603,008-bits of memory are organized as 8,192 pages of 512 bytes or 528 bytes each. In addition to the main memory, the AT45DB321D also contains two SRAM buffers of 512/528 bytes each. These buffers allow the receiving of data while a page in the main memory is being reprogrammed, as well as the writing of a continuous data stream. EEPROM (electrically erasable and programmable read-only memory) emulation (bit or byte alterability) is easily handled with a self-contained, three-step read-modify-write operation. Unlike conventional flash memories, which are accessed randomly with multiple address lines and a parallel interface, DataFlash® devices use a RapidS serial interface to sequentially access its data. The simple sequential access dramatically reduces active pin count, facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and industrial applications where high density, low pin count, low voltage and low power are essential. To allow for simple, in-system reprogrammability, the AT45DB321D does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB321D is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the serial input (SI), serial output (SO), and serial clock (SCK) lines. All programming and erase cycles are self timed. Figure 1-1. Pin configurations and pinouts. MLF(1) (VDFN) Top View Note: 1. The metal pad on the bottom of the MLF package is floating. This pad can be a “No Connect” or connected to GND. SOIC Top View BGA Package Ball-out Top View TSOP: Type 1 Top View Note: TSOP package is not recommended for new designs. Future die shrinks will support 8-pin packages only. SI SCK RESET CS SO GND VCC WP 8 7 6 5 1 2 3 4 1 2 3 4 8 7 6 5 SI SCK RESET CS SO GND VCC WP NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCC GND SCK CS RDY/BSY WP SI SO RESET 1 2 3 4 5 A B C D E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RDY/BUSY RESET WP NC NC VCC GND NC NC NC CS SCK SI SO NC NC NC NC NC NC NC NC NC NC NC NC NC NC |
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