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AT25DN256

DS-25DN256–039B–5/2014

1.

Description

The Adesto

based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The

flexible erase architecture of the AT25DN256, with its page erase granularity it is ideal for data storage as well, eliminating the

need for additional data storage devices.

The erase block sizes of the AT25DN256 have been optimized to meet the needs of today's code and data storage applications.

By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because certain code modules

and data storage segments must reside by themselves in their own erase regions, the wasted and unused memory space that

occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space

efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device

density.

The device also contains a specialized OTP (One-Time Programmable) Security Register that can be used for purposes such as

unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc.

Specifically designed for use in many different systems, the AT25DN256 supports read, program, and erase operations with a

wide supply voltage range of 2.3V to 3.6V. No separate voltage is required for programming and erasing.

2.

Pin Descriptions and Pinouts

Table 2-1.

Pin Descriptions

Symbol

Name and Function

Asserted

State

Type

CS

CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the

device will be deselected and normally be placed in standby mode (not Deep Power-Down mode),

and the SO pin will be in a high-impedance state. When the device is deselected, data will not be

accepted on the SI pin.

A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition

is required to end an operation. When ending an internally self-timed operation such as a program

or erase cycle, the device will not enter the standby mode until the completion of the operation.

Low

Input

SCK

SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of

data to and from the device. Command, address, and input data present on the SI pin is always

latched in on the rising edge of SCK, while output data on the SO pin is always clocked out on the

falling edge of SCK.

-

Input

SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input

including command and address sequences. Data on the SI pin is always latched in on the rising

edge of SCK.

other pins to allow two bits of data on (I/O

To maintain consistency with the SPI nomenclature, the SI (I/O

pin unless specifically addressing the Dual-I/O modes in which case it will be referenced as I/O

0.

Data present on the SI pin will be ignored whenever the device is deselected (CS is deasserted).

-

Input/

Output

SO

SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is

always clocked out on the falling edge of SCK.

With the Dual-Output Read commands, the SO Pin remains an output pin (I/O

pin unless specifically addressing the Dual-I/O modes in which case it will be referenced as I/O

1.

The SO pin will be in a high-impedance state whenever the device is deselected (CS is

deasserted).

-

Input/

Output