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AT25DF641A-MH-T Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers |
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AT25DF641A-MH-T Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers |
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7 / 58 page  7 AT25DF641A [DATASHEET] 8793D–DFLASH–5/2013 5. Device Operation The AT25DF641A is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI master. The SPI master communicates with the AT25DF641A via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO). The AT25DF641A features a Dual-Input Program mode in which the SO pin becomes an input. Similarly, the device also features a Dual-Output Read mode in which the SI pin becomes an output. In the Dual-Input Byte/Page Program command description, the SO pin will be referred to as the SOI (Serial Output/Input) pin, and in the Dual-Output Read Array command, the SI pin will be referenced as the SIO (Serial Input/Output) pin. The SPI protocol defines a total of four modes of operation (Mode 0, 1, 2, or 3) with each mode differing in respect to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25DF641A supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge of SCK. Figure 5-1. SPI Mode 0 and 3 6. Commands and Addressing A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted, the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction-dependent information, such as address and data bytes, would then be clocked out by the host controller. All opcode, address, and data bytes are transferred with the Most-Significant Bit (MSB) first. An operation is ended by deasserting the CS pin. Opcodes not supported by the AT25DF641A will be ignored by the device and no operation will be started. The device will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then reasserted). In addition, if the CS pin is deasserted before complete opcode and address information is sent to the device, then no operation will be performed, and the device will simply return to the idle state and wait for the next operation. Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0. Since the upper address limit of the AT25DF641A memory array is 7FFFFFh, address bit A23 is always ignored by the device. SCK CS SI SO MSB LSB MSB LSB |
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