8

AT25DF512C

DS-25DF512C–030A–4/2014

To perform the Read Array operation, the CS pin must first be asserted and the appropriate opcode (0Bh or 03h) must be

clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the

starting address location of the first byte to read within the memory array. Following the three address bytes, an

additional dummy byte needs to be clocked into the device if the 0Bh opcode is used for the Read Array operation.

After the three address bytes (and the dummy byte if using opcode 0Bh) have been clocked in, additional clock cycles

will result in data being output on the SO pin. The data is always output with the MSB of a byte first. When the last byte

(00FFFFh) of the memory array has been read, the device will continue reading back at the beginning of the array

(000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array.

Deasserting the CS pin will terminate the read operation and put the SO pin into high-impedance state. The CS pin can

be deasserted at any time and does not require a full byte of data be read.

Figure 7-1.

Read Array - 03h Opcode

Figure 7-2.

Read Array - 0Bh Opcode

7.2

Dual-Output Read Array

The Dual-Output Read Array command is similar to the standard Read Array command and can be used to sequentially

read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has

been specified. Unlike the standard Read Array command, however, the Dual-Output Read Array command allows two

bits of data to be clocked out of the device on every clock cycle, rather than just one.

The Dual-Output Read Array command can be used at any clock frequency, up to the maximum specified by f

perform the Dual-Output Read Array operation, the CS pin must first be asserted and then the opcode 3Bh must be

clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the

location of the first byte to read within the memory array. Following the three address bytes, a single dummy byte must

also be clocked into the device.

After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being

output on both the SO and SIO pins. The data is always output with the MSB of a byte first and the MSB is always output

on the SO pin. During the first clock cycle, bit seven of the first data byte is output on the SO pin, while bit six of the same

data byte is output on the SIO pin. During the next clock cycle, bits five and four of the first data byte are output on the SO

SCK

CS

SI

SO

MSB

MSB

23

1

0

00000011

67

5

410 11

9

812

37 38

33

36

35

34

31 32

29 30

39 40

OPCODE

AAAA

AAA

A

A

MSB

MSB

DDDDDDD

D

D

D

ADDRESS BITS A23-A0

DATA BYTE 1

HIGH-IMPEDANCE

K

S

I

O

MSB

MSB

23

1

0

00001011

67

5

410 11

9

812

39

42 43

41

40

37 38

33

36

35

34

31 32

29 30

44

47 48

46

45

OPCODE

AAAA

AAA

A

A

MSB

XXXXXXX

X

MSB

MSB

DDDDDDD

D

D

D

ADDRESS BITS A23-A0

DON'T CARE

DATA BYTE 1

HIGH-IMPEDANCE