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NCP6132ADMNR2G Datasheet(PDF) 7 Page - ON Semiconductor

Part # NCP6132ADMNR2G
Description  Dual Output 3 Phase & 2 Phase Controller with Single SVID Interface for Desktop and Notebook CPU Applications
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NCP6132ADMNR2G Datasheet(HTML) 7 Page - ON Semiconductor

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NCP6132A, NCP6132B
http://onsemi.com
7
Table 5. ELECTRICAL CHARACTERISTICS Unless otherwise stated: −10°C < TA< 100°C; VCC = 5.0 V; CVCC = 0.1 mF
Parameter
Test Conditions
Min
Typ
Max
Units
CURRENT SUMMING AMPLIFIER
Offset Voltage (Vos)
−300
300
mV
Input Bias Current (CSSUM)
CSSUM = CSREF = 1 V
−7.5
7.5
nA
Open Loop Gain
80
dB
Current Sense Unity Gain Bandwidth
CL = 20 pF to GND,
RL = 10 kW to GND
10
MHz
Maximum CSCOMP (A) Output Voltage
Isource = 2 mA
3.5
−
−
V
Minimum CSCOMP(A) Output Voltage
Isink = 500 mA
−
−
0.1
V
CURRENT BALANCE AMPLIFIER
Input Bias Current
CSPx = CSREF = 1.2 V
−50
−
50
nA
Common Mode Input Voltage Range
CSPx = CSREF
0
−
2.0
V
Differential Mode Input Voltage Range
CSREF = 1.2 V
−100
−
100
mV
Input Offset Voltage Matching
CSPx = CSREF = 1.2 V,
Measured from the average
−1.5
−
1.5
mV
Current Sense Amplifier Gain
0 V < CSPx − CSREF < 0.1 V,
−10°C ~ 85°C
−10°C ~ 100°C
5.7
5.5
6.0
6.0
6.3
6.3
V/V
Multiphase Current Sense Gain Matching
CSREF = CSP = 10 mV to 30 mV
−3
3
%
−3 dB Bandwidth
8
MHz
BIAS SUPPLY
VCC Quiescent Current
EN = high
20
27
35
mA
EN = low
10
70
mA
UVLO Threshold
VCC rising
4.5
V
VCC falling
4.0
V
VCC UVLO Hysteresis
200
mV
VDDBP Quiescent Current
EN = Low
EN = High
0.8
12.0
mA
DAC SLEW RATE
Soft Start Slew Rate
2.33
mv/ms
Slew Rate Slow
3.5
mv/ms
Slew Rate Fast
13.5
mv/ms
AUX Soft Start Slew Rate
2.33
mv/ms
AUX Slew Rate Slow
3.5
mv/ms
AUX Slew Rate Fast
13.5
mv/ms
ENABLE INPUT
Enable High Input Leakage Current
External 1k pull−up to 3.3 V
−
1.0
mA
Upper Threshold
VUPPER
0.8
V
Lower Threshold
VLOWER
0.35
V
Total Hysteresis
VUPPER – VLOWER
95
mV
Enable Delay Time
Measure time from Enable transitioning HI
to when DRON goes high, Vboot is not 0 V
5.0
ms
3. Guaranteed by design/characterization, not in production test
4. Guaranteed by characterization


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