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EM636327Q-8 Datasheet(PDF) 1 Page - Etron Technology, Inc. |
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EM636327Q-8 Datasheet(HTML) 1 Page - Etron Technology, Inc. |
1 / 78 page EtronTech EM636327 Etron Technology, Inc. 1F, No. 1, Prosperity Rd. 1, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C TEL: (886)-3-5782345 FAX: (886)-3-5779001 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. 512K x 32 High Speed Synchronous Graphics DRAM(SGRAM) Preliminary (12/98) Features • Fast access time from clock: 5/5/5.5/6.5/7.5 ns • Fast clock rate: 183/166/143/125/100 MHz • Fully synchronous operation • Internal pipelined architecture • Dual internal banks(256K x 32-bit x 2-bank) • Programmable Mode and Special Mode registers - CAS# Latency: 1, 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst-Read-Single-Write - Load Color or Mask register • Burst stop function • Individual byte controlled by DQM0-3 • Block write and write-per-bit capability • Auto Refresh and Self Refresh • 2048 refresh cycles/32ms • Single +3.3V±0.3V power supply • Interface: LVTTL • JEDEC 100-pin Plastic package -QFP (body thickness=2.8mm) -TQFP1.4 (body thickness=1.4mm) -TQFP1.0 (body thickness=1.0mm) Overview Key Specifications EM636327 - 55/6/7/8/10 tCK3 Clock Cycle time(min.) 5.5/6/7/8/10 ns tRAS Row Active time(max.) 32/36/42/48/60 ns tAC1 Access time from Read command 7/8/13/18/23 ns tAC3 Access time from CLK(max.) 5/5/5.5/6.5/7.5 ns tRC Row Cycle time(min.) 48/54/63/72/90 ns Ordering Information Part Number Frequency Package EM636327Q-10 100MHz QFP EM636327R-10 100MHz QFP (Reverse) EM636327TQ-10 100MHz TQFP1.4 EM636327JT-10 100MHz TQFP1.0 EM636327Q-8 125MHz QFP EM636327R-8 125MHz QFP (Reverse) EM636327TQ-8 125MHz TQFP1.4 EM636327JT-8 125MHz TQFP1.0 EM636327Q-7 143MHz QFP EM636327TQ-7 143MHz TQFP1.4 EM636327Q-6 166MHz QFP EM636327TQ-6 166MHz TQFP1.4 EM636327Q-55 183MHz QFP EM636327TQ-55 183MHz TQFP1.4 The EM636327 SGRAM is a high-speed CMOS synchronous graphics DRAM containing 16 Mbits. It is internally configured as a dual 256K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 256K x 32 bit banks is organized as 1024 rows by 256 columns by 32 bits. Read and write accesses to the SGRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The EM636327 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, EM636327 features the write-per-bit and the masked block write functions. By having a programmable mode register and special mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth, and when combined with special graphics functions result in a device particularly well suited to high performance graphics applications. |
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