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EM636327JT-10 Datasheet(PDF) 9 Page - Etron Technology, Inc. |
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EM636327JT-10 Datasheet(HTML) 9 Page - Etron Technology, Inc. |
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9 / 78 page  EtronTech EM636327 Preliminary 9 December 1998 CLK C OM M A ND CAS# latency=2 tCK2, DQ's T0 T1 T2 T3 T4 T5 T6 T7 T8 READ A NOP NOP NOP NOP Activate NOP NOP Precharge CAS# latency=3 tCK3, DQ's DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 ADDRESS CAS# latency=1 tCK1, DQ's tRP Bank, Col A Bank(s) Bank, Row Read to Precharge (CAS# Latency = 1, 2, 3) 6 Read and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "H", DSF = "L", BS = Bank, A9 = "H", A0-A7 = Column Address) The Read and AutoPrecharge command automatically performs the precharge operation after the read operation. Once this command is given, any subsequent command cannot occur within a time delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in this command and the auto precharge function is ignored. 7 Write command (RAS# = "H", CAS# = "L", WE# = "L", DSF = "L", BS = Bank, A9 = "L", A0-A7 = Column Address) The Write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank. The bank must be active for at least tRCD(min.) before the Write command is issued. During write bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data elements will be registered on each successive positive clock edge (refer to the following figure). The DQs remain with high-impedance at the end of the burst unless another command is initiated. The burst length and burst sequence are determined by the mode register, which is already programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). CLK C OM M A ND T0 T1 T2 T3 T4 T5 T6 T7 T8 DIN A3 NOP WRITE A NOP NOP NOP NOP NOP NOP NOP DIN A0 DIN A1 DIN A2 DQ0 - DQ3 The first data element and the write are registered on the same clock edge. Extra data is masked. don't care Burst Write Operation (Burst Length = 4, CAS# Latency = 1, 2, 3) Any Write performed to a row that was opened via an BankActivate & Masked Write Enable command is a masked write (Write-Per-Bit). Data is written to the 32 cells (bits) at the selected column location subject to the data stored in the Mask register. The overall mask consists of the DQM inputs, which mask on a per-byte basis, and the Mask register, which masks also on a per-bit basis. This is shown in the following block diagram. |
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