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FT24C08A-UPG-T Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers |
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FT24C08A-UPG-T Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers |
4 / 20 page 24C04A, 24C08A, 24C16A (C) STOP CONDITION With SCL VIH, a SDA transition from low to high is interpreted as a STOP condition. All valid read or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after a read command. A STOP condition after page or byte write command will trigger the chip into the STANDBY mode after the self- timed internal programming finish. (D) ACKNOWLEDGE The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The ACKNOWLEDGE signal occurs on the 9th serial clock after each word. (E) STANDBY MODE The EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP bit in read mode, or after completing a self-time internal programming operation. Figure 1: Timing diagram for START and STOP conditions SCL SDA START Condition Data Data Valid Transition STOP Condition Figure 2: Timing diagram for output ACKNOWLEDGE START Condition SCL Data in Data out ACK DS3001M-page4 © 2009 Fremont Micro Devices Inc. |
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