Product Specification

PE43502

Page 5 of 11

Document No. 70-0247-06

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©2008-2009 Peregrine Semiconductor Corp. All rights reserved.

Table 5. Control Voltage

State

Bias Condition

Low

0 to +1.0 Vdc at 2

µA (typ)

High

+2.6 to +5 Vdc at 10

µA (typ)

Table 6. Latch and Clock Specifications

Latch Enable

Function

X

Shift Register Clocked

↑

Contents of shift register

transferred to attenuator core

Shift Clock

↑

X

Attenuation Word

Attenuation

Setting

RF1-RF2

D7

D6

D5

D4

D3

D2

D1

D0

(LSB)

L

L

L

L

L

L

L

L

Reference I.L.

L

L

L

L

L

L

H

L

0.5 dB

L

L

L

L

L

H

L

L

1 dB

L

L

L

L

H

L

L

L

2 dB

L

L

L

H

L

L

L

L

4 dB

L

L

H

L

L

L

L

L

8 dB

L

L

H

H

H

H

H

L

15.5 dB

Table 8. Attenuation Word Truth Table

Table 9. Serial Register Map

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

D7

D6

D5

D4

D3

D2

D1

D0

Attenuation Word

LSB (first in)

MSB (last in)

Bits must be set to logic low

Attenuation Word is derived directly from the attenuation value. For example, to program the 12.5 dB state:

Attenuation Word: Multiply by 4 and convert to binary

→ 4 * 12.5 dB → 50 → 00110010

Serial Input: 00110010

Parallel Control Setting

Attenuation Setting

RF1-RF2

D5

D4

D3

D2

D1

L

L

L

L

L

Reference I.L.

L

L

L

L

H

0.5 dB

L

L

L

H

L

1 dB

L

L

H

L

L

2 dB

L

H

L

L

L

4 dB

H

L

L

L

L

8 dB

H

H

H

H

H

15.5 dB

Table 7. Parallel Truth Table

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