DS92CK16

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SNAS044C – NOVEMBER 1999 – REVISED APRIL 2013

DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

Check for Samples: DS92CK16

1

FEATURES

DESCRIPTION

The DS92CK16 1 to 6 Clock Buffer/Bus Transceiver

2

•

Master/Slave Clock Selection in a Backplane

is a one to six CMOS differential clock distribution

Application

device utilizing Bus Low Voltage Differential Signaling

•

125 MHz Operation (Typical)

(BLVDS) technology. This clock distribution device is

•

100 ps Duty Cycle Distortion (Typical)

designed for applications requiring ultra low power

dissipation, low noise, and high data rates. The

•

50 ps Channel to Channel Skew (Typical)

BLVDS side is a transceiver with a separate channel

•

3.3V Power Supply Design

acting as a return/source clock.

•

Glitch-free Power on at CLKI/O Pins

The DS92CK16 accepts LVDS (300 mV typical)

•

Low Power Design (20 mA @ 3.3V Static)

differential input levels, and translates them to 3V

•

Accepts Small Swing (300 mV Typical)

CMOS output levels. An output enable pin OE , when

Differential Signal Levels

•

Industrial Temperature Operating Range (-40°C

The device can be used as a source synchronous

to +85°C)

driver.

The

selection

of

the

source

driving

is

•

Available in 24-pin TSSOP Packaging

can be the master clock, driving the inputs of other

clock I/O pins in a multipoint environment. Easy

master/slave clock selection is achieved along a

backplane.

Function Diagram and Truth Table

Table 1. Receive Mode Truth Table

INPUT

OUTPUT

OE

DE

(CLKI/O+)–(CLKI/O

−)

H

H

X

X

H

L

H

X

VID

≥ 0.07V

H

L

H

X

VID

≤ −0.07V

L

1

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2

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PRODUCTION DATA information is current as of publication date.

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Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.