3D3438x-250 datasheet(5/6 Pages) DATADELAY

Part #	3D3438x-250

Description	MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7438)

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Manufacturer	DATADELAY [Data Delay Devices, Inc.]

Direct Link	http://www.datadelay.com

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5 / 6 page

3D3438

Doc #10005

DATA DELAY DEVICES, INC.

5

7/8/2010

3 Mt. Prospect Ave. Clifton, NJ 07013

DEVICE SPECIFICATIONS

TABLE 3: ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

DC Supply Voltage

VDD

-0.3

7.0

V

Input Pin Voltage

VIN

-0.3

VDD+0.3

V

Input Pin Current

IIN

-10

10

mA

25C

Storage Temperature

TSTRG

-55

150

C

Lead Temperature

TLEAD

300

C

10 sec

TABLE 4: DC ELECTRICAL CHARACTERISTICS

(-40C to 85C, 3.0V to 3.6V)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Static Supply Current*

IDD

3.0

5.0

mA

Addr = 128

High Level Input Voltage

VIH

2.0

V

Low Level Input Voltage

VIL

0.8

V

High Level Input Current

IIH

1.0

A

VIH = VDD

Low Level Input Current

IIL

1.0

A

VIL = 0V

High Level Output

Current

IOH

-15.0

-4.0

mA

VDD = 3.0V

VOH = 2.4V

Low Level Output Current

IOL

4.0

15.0

mA

VDD = 3.0V

VOL = 0.4V

Output Rise & Fall Time

TR & TF

2.0

2.5

ns

CLD = 5 pf

*IDD(Dynamic) = CLD * VDD * F

Input Capacitance = 10 pf typical

where:

CLD = Average capacitance load/line (pf)

Output Load Capacitance (CLD) = 25 pf max

F = Input frequency (GHz)

TABLE 5: AC ELECTRICAL CHARACTERISTICS

(-40C to 85C, 3.0V to 3.6V)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Clock Frequency

fC

80

MHz

Enable Width

tEW

10

ns

Clock Width

tCW

10

ns

Data Setup to Clock

tDSC

10

ns

Data Hold from Clock

tDHC

3

ns

Data Setup to Enable

tDSE

10

ns

Data Hold from Enable

tDHE

3

ns

Enable to Serial Output Valid

tEQV

20

ns

Enable to Serial Output High-Z

tEQZ

20

ns

Clock to Serial Output Valid

tCQV

20

ns

Clock to Serial Output Invalid

tCQX

10

ns

Enable Setup to Clock

tES

10

ns

Enable Hold from Clock

tEH

10

ns

Parallel Input Valid to Delay Valid

tPDV

20

40

ns

Parallel Input Change to Delay Invalid

tPDX

0

ns

Enable to Delay Valid

tEDV

35

45

ns

Enable to Delay Invalid

tEDX

0

ns

Input Pulse Width

tWI

40

% of Delay

See Table 1

Input Period

Period

80

% of Delay

See Table 1

Input to Output Delay

tPLH, tPHL

ns

See Table 2

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