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EDS5116ABTA-6B Datasheet(PDF) 1 Page - Elpida Memory |
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EDS5116ABTA-6B Datasheet(HTML) 1 Page - Elpida Memory |
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1 / 52 page  Document No. E0250E10 (Ver. 1.0) Date Published March 2002 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2002 PRELIMINARY DATA SHEET 512M bits SDRAM EDS5104ABTA (128M words ×××× 4 bits) EDS5108ABTA (64M words ×××× 8 bits) EDS5116ABTA (32M words ×××× 16 bits) Description The EDS5104AB is a 512M bits SDRAM organized as 33,554,432 words × 4 bits × 4 banks. The EDS5108AB is a 512M bits SDRAM organized as 16,777,216 words × 8 bits × 4 banks. The EDS5116AB is a 512M bits SDRAM organized as 8,388,608 words × 16 bits × 4 banks. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54- pin plastic TSOP (II). Features • 3.3V power supply • Clock frequency: 166MHz/133MHz (max.) • LVTTL interface • Single pulsed /RAS • 4 banks can operate simultaneously and independently • Burst read/write operation and burst read/single write operation capability • Programmable burst length (BL): 1, 2, 4, 8, full page • 2 variations of burst sequence Sequential (BL = 1, 2, 4, 8, full page) Interleave (BL = 1, 2, 4, 8) • Programmable /CAS latency (CL): 2, 3 • Byte control by DQM : DQM (EDS5104AB, EDS5108AB) : UDQM, LDQM (EDS5116AB) • Refresh cycles: 8192 refresh cycles/64ms • 2 variations of refresh Auto refresh Self refresh Pin Configurations /xxx indicates active low signal. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM /WE /CAS /RAS /CS BA0 BA1 A10 A0 A1 A2 A3 VDD 54-pin TSOP (Top view) VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDD NC /WE /CAS /RAS /CS BA0 BA1 A10 A0 A1 A2 A3 VDD VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC VDD NC /WE /CAS /RAS /CS BA0 BA1 A10 A0 A1 A2 A3 VDD VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC VSS NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS X 8 X 16 X 4 Address input Bank select address Data-input/output Chip select Row address strobe Column address strobe Write enable A0 to A12, BA0, BA1 DQ0 to DQ15 /CS /RAS /CAS /WE Input/output mask Clock enable Clock input Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection DQM CKE CLK VDD VSS VDDQ VSSQ NC |
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