EDE5108GBSA-4A-E datasheet(7/56 Pages) ELPIDA

Part #	EDE5108GBSA-4A-E

Description	512M bits DDR-II SDRAM

Download	56 Pages

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Preliminary Data Sheet E0249E30 (Ver. 3.0)

7

Pin Capacitance (TA = 25°C, VDD, VDDQ = 1.8V ± 0.1V)

Parameter

Symbol

Pins

min.

Typ

max.

Unit

Notes

CLK input pin capacitance

CCK

CK

1.5

2.0

2.5

pF

1

Input pin capacitance

CIN

/RAS, /CAS,

/WE, /CS,

CKE. ODT,

Address

1.5

2.0

2.5

pF

1

Input/output pin capacitance

CI/O

DQ, DQS, /DQS,

UDQS, /UDQS,

LDQS, /LDQS,

/RDQS, /RDQS,

DM, UDM, LDM

3.0

3.5

4.0

pF

2

Notes: 1. Matching within 0.25pF.

2. Matching within 0.50pF.

AC Characteristics (TA = 0 to +70

°°°°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)

-5A

-4A

Frequency (Mbps)

533

400

Parameter

Symbol

min.

max.

min.

max.

Unit

Notes

DQ output access time from CK, /CK

tAC

–500

+500

–600

+600

ps

DQS output access time from CK, /CK

tDQSCK

–450

+450

–500

+500

ps

CK high-level width

tCH

0.45

0.55

0.45

0.55

tCK

CK low-level width

tCL

0.45

0.55

0.45

0.55

tCK

CK half period

tHP

min.

(tCL, tCH)



min.

(tCL, tCH)



ps

Clock cycle time

tCK

3750

8000

5000

8000

ps

DQ and DM input hold time

tDH

350



400



ps

DQ and DM input setup time

tDS

350



400



ps

Control and Address input pulse width

for each input

tIPW

0.6



0.6



tCK

DQ and DM input pulse width for each

input

tDIPW

0.35



0.35



tCK

Data-out high-impedance time from

CK,/CK

tHZ



tAC max.



tAC max.

ps

Data-out low-impedance time from

CK,/CK

tLZ

tAC min.

tAC max.

tAC min.

tAC max.

ps

DQS-DQ skew for DQS and associated

DQ signals

tDQSQ



300



350

ps

DQ hold skew factor

tQHS



400



450

ps

DQ/DQS output hold time from DQS

tQH

tHP – tQHS



tHP – tQHS



ps

Write command to first DQS latching

transition

tDQSS

WL – 0.25

WL + 0.25

WL – 0.25

WL + 0.25

tCK

DQS input high pulse width

tDQSH

0.35



0.35



tCK

DQS input low pulse width

tDQSL

0.35



0.35



tCK

DQS falling edge to CK setup time

tDSS

0.2



0.2



tCK

DQS falling edge hold time from CK

tDSH

0.2



0.2



tCK

Mode register set command cycle time

tMRD

2



2



tCK

Write preamble setup time

tWPRES

0



0



tCK

Write postamble

tWPST

0.4

0.6

0.4

0.6

tCK

Write preamble

tWPRE

0.25



0.25



tCK

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