EDL1216AASA datasheet(8/59 Pages) ELPIDA

Part #	EDL1216AASA

Description	128M bits Mobile RAM

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Manufacturer	ELPIDA [Elpida Memory]

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EDL1216AASA

Data Sheet E0196E30 (Ver. 3.0)

8

Synchronous Characteristics

Parameter

Symbol

min.

max.

Unit

Note

Clock cycle time

(CL= 2)

tCK2

10

—

ns

(CL= 3)

tCK3

7.5

—

ns

Access time from CLK

(CL= 2)

tAC2

—

6

ns

1

(CL= 3)

tAC3

—

5.4

ns

1

CLK high level width

tCH

2.5

—

ns

CLK low level width

tCL

2.5

—

ns

Data-out hold time

tOH

2.5

—

ns

1

Data-out low-impedance time

tLZ

0

—

ns

Data-out high-impedance time

(CL= 2)

tHZ2

2.5

6

ns

(CL= 3)

tHZ3

2.5

5.4

ns

Data-in setup time

tDS

1.5

—

ns

Data-in hold time

tDH

0.8

—

ns

Address setup time

tAS

1.5

—

ns

Address hold time

tAH

0.8

—

ns

CKE setup time

tCKS

1.5

—

ns

CKE hold time

tCKH

0.8

—

ns

CKE setup time (Power down exit)

tCKSP

1.5

—

ns

Command (/CS, /RAS, /CAS, /WE,

UDQM, LDQM) setup time

tCMS

1.5

—

ns

Command (/CS, /RAS, /CAS, /WE,

UDQM, LDQM) hold time

tCMH

0.8

—

ns

Note: 1. Output load.

Output

Z = 50

Ω

30 pF

Output load

Asynchronous Characteristics

Parameter

Symbol

min.

max.

Unit

Notes

ACT to REF/ACT command period (operation) tRC

67.5



ns

ACT to REF/ACT command period (refresh)

tRC1

67.5



ns

ACT to PRE command period

tRAS

45

120000

ns

PRE to ACT command period

tRP

20



ns

Delay time ACT to READ/WRITE command

tRCD

20



ns

ACT (one) to ACT (another) command period

tRRD

15



ns

Data-in to PRE command period

tDPL

15



ns

Data-in to ACT (REF) command period

(Auto precharge)

(CL = 2)

TDAL2

2CLK + 20



ns

(CL = 3)

TDAL3

2CLK + 20



ns

Mode register set cycle time

tRSC

2



CLK

Transition time

tT

0.5

30

ns

Refresh time (4,096 refresh cycles)

tREF

64



ms

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