CDCV850

2.5-V PHASE LOCK LOOP CLOCK DRIVER

WITH 2-LINE SERIAL INTERFACE

SCAS647D − OCTOBER 2000 − REVISED APRIL 2013

6

POST OFFICE BOX 655303

timing requirements over recommended ranges of supply voltage and operating free-air

temperature

MIN

MAX

UNIT

Clock frequency

60

140

MHz

Input clock duty cycle

40%

60%

Stabilization time†

10

μs

fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,

and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under

SSC application.

timing requirements for the 2-line serial interface over recommended ranges of operating

free-air temperature and VDDI from 3.3 V to 3.6 V (see Figure 10)

MIN

MAX

UNIT

SCLK frequency

100

kHz

Bus free time

4.7

μs

START setup time†

4.7

μs

START hold time†

4.0

μs

SCLK low pulse duration

4.7

μs

SLCK high pulse duration

4.0

μs

SDATA input rise time

1000

ns

SDATA input fall time

300

ns

SDATA setup time

250

ns

SDATA hold time

0

ns

STOP setup time

4

μs