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CDCV850IDGGRG4 Datasheet(PDF) 6 Page - Texas Instruments |
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CDCV850IDGGRG4 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 20 page CDCV850 2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE SCAS647D − OCTOBER 2000 − REVISED APRIL 2013 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature MIN MAX UNIT f(CLK) Clock frequency 60 140 MHz Input clock duty cycle 40% 60% Stabilization time† 10 μs † Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application. timing requirements for the 2-line serial interface over recommended ranges of operating free-air temperature and VDDI from 3.3 V to 3.6 V (see Figure 10) MIN MAX UNIT f(SCLK) SCLK frequency 100 kHz t(BUS) Bus free time 4.7 μs tsu(START) START setup time† 4.7 μs th(START) START hold time† 4.0 μs tw(SCLL) SCLK low pulse duration 4.7 μs tw(SCLH) SLCK high pulse duration 4.0 μs tr(SDATA) SDATA input rise time 1000 ns tf(SDATA) SDATA input fall time 300 ns tsu(SDATA) SDATA setup time 250 ns th(SDATA) SDATA hold time 0 ns tsu(STOP) STOP setup time 4 μs † This conforms to I2C specification, version 2.1. |
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