ATA-Disk Module 4

AP-FMxxxxL20XXS-XXXXT

7

© 2011 Apacer Technology Inc.

Rev. 1.1

5. Flash Management

5.1 Intelligent Endurance Design

5.1.1 Advanced wear-leveling algorithms

The NAND flash devices are limited by a certain number of write cycles. When using a file system,

frequent file table updates is mandatory. If some area on the flash wears out faster than others, it would

significantly reduce the lifetime of the whole device, even if the erase counts of others are far from the

write cycle limit. Thus, if the write cycles can be distributed evenly across the media, the lifetime of the

media can be prolonged significantly. The scheme is achieved both via buffer management and Apacer-

specific advanced wear leveling to ensure that the lifetime of the flash media can be increased, and the

disk access performance is optimized as well.

5.1.2 S.M.A.R.T. technology

S.M.A.R.T. is an acronym for Self-Monitoring, Analysis and Reporting Technology, an open standard

allowing disk drives to automatically monitor their own health and report potential problems. It protects the

user from unscheduled downtime by monitoring and storing critical drive performance and calibration

parameters. Ideally, this should allow taking proactive actions to prevent impending drive failure. Apacer

SMART feature adopts the standard SMART command B0h to read data from the drive. When the Apacer

SMART Utility running on the host, it analyzes and reports the disk status to the host before the device is

in critical condition.

5.1.3 Built-in hardware ECC

The ATA-Disk Module uses BCH Error Detection Code (EDC) and Error Correction Code (ECC)

algorithms which correct 6 or 12 random bits of error for each 512-Byte block of data and 12 or 24

random bits of error for each 1K-Byte block of data. High performance is fulfilled through hardware-based

error detection and correction.

5.1.4 Enhanced data integrity

The properties of NAND flash memory make it ideal for applications that require high integrity while

operating in challenging environments. The integrity of data to NAND flash memory is generally

maintained through ECC algorithms and bad block management. Flash controllers can support up to 8

bits ECC capability for accuracy of data transactions, and bad block management is a preventive

mechanism from loss of data by retiring unusable media blocks and relocating the data to the other blocks,

along with the integration of advanced wear leveling algorithms, so that the lifespan of device can be

expanded.