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APSDM016GA5AN-PC Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers |
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APSDM016GA5AN-PC Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers |
4 / 22 page SATA-Disk Module 4 APSDMxxxxX5AN-PXXX 3 © 2013 Apacer Technology Inc. Rev. 1.5 1. General Description Apacer’s SATA-Disk Module 4 (SDM4) is a high-performance, embedded SSD designed to replace the conventional SATA hard disk drive. SDM SSD can be plugged into a standard Serial ATA connectors commonly found in desktops, IT-STB, industrial PC and thin client systems. Apacer’s SDM4 is built in with an efficient microcontroller that drives the potential of NAND flashy and delivers optimal performance. With its compact form factor and SATA II interface, this product is well suited for embedded flash storage applications offering customizable and expanded functionalities as well as more cost-effective designs, better performance and increased reliability. SDM4 Series is designed to work at 5 Volts and uses a standard SATA driver that complies with major operating systems such as Microsoft’s Windows series. Featuring technologies as Apacer-specific Wear- leveling algorithms, S.M.A.R.T, bad block management, Power Failure Management, ATA Secure Erase, and TRIM, Apacer assures users of a versatile device on data storage. 1.1 Performance-Optimized Controller The heart of SDM4 is the Flash controller, which translates standard SATA signals into the data and controls of the flash media. The SATA and Flash Management controller are specifically designed to attain high data throughput from the host to the flash. 1.1.1 Power Management The controller comes with SATA physical interface (PHY) that takes a significant part of the total power budget of the host or other connected electronics. SATA interface provides the means to place the PHY into lowered power modes. When the parts of power for PHY are shut down to reserve power supply, the ability of the SATA interfaced device to respond to command can be affected. Thus, the SATA protocol is implemented with the capability to track the power modes of the devices and require the additional latency to wake up PHY from lowered power modes. 1.1.2 RAM The controller is implemented with RAM as a data buffer to optimize data transfer between the host and the flash media. |
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