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46DR81280A Datasheet(PDF) 8 Page - Integrated Silicon Solution, Inc |
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46DR81280A Datasheet(HTML) 8 Page - Integrated Silicon Solution, Inc |
8 / 28 page IS43/46DR81280A, IS43/46DR16640A Integrated Silicon Solution, Inc. – www.issi.com – 8 Rev. D, 08/30/2011 Extended Mode Register 2 (EMR[2]) Diagram Address Field Mode Register BA2 0 BA1 1 BA0 0 A13 (1) 0 A7 0 1 A2 A1 A0 BA[2:0] 0 0 0 All combinations 0 0 1 000, 001, 010, 011 0 1 0 000, 001 0 1 1 000 1 0 0 010, 011, 100, 101, 110, 111 1 0 1 100, 101, 110, 111 1 1 0 110, 111 1 1 1 111 A2 PASR (3) Quarter Array 1/8 array A1 3/4 array Half array A0 Quarter array 1/8 array A4 (1) 0 Partial Array Self Refresh for 8 Banks A3 (1) 0 Full Array Half Array A6 (1) 0 A5 (1) 0 A8 (1) 0 High Temperature Self-Refresh Rate Enable A7 SRFt Disable Enable (2) A10 (1) 0 A9 (1) 0 A12 (1) 0 A11 (1) 0 Notes: 1. A3‐A6, and A8‐A13 are reserved for future use and must be set to 0 when programming the EMR[2]. 2. Only Industrial and Automotive grade devices support the high temperature Self‐Refresh Mode. The controller can set the EMR (2) [A7] bit to enable this self‐ refresh rate if Tc > 85°C while in self‐refresh operation. TOPER may not be violated. 3. If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified address range will be lost if self refresh is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued. DDR2 Extended Mode Register 3 (EMR[3]) Setting No function is defined in extended mode register 3. The default value of the extended mode register 3 is not defined. Therefore, the extended mode register 3 must be programmed during initialization for proper operation. DDR2 Extended Mode Register 3 (EMR[3]) Diagram BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0* 1 1 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* Address Field Mode Register Note: All bits in EMR[3] except BA0 and BA1 are reserved for future use and must be set to 0 when programming the EMR[3]. |
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