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SI3402 Datasheet(PDF) 11 Page - List of Unclassifed Manufacturers |
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SI3402 Datasheet(HTML) 11 Page - List of Unclassifed Manufacturers |
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11 / 22 page  Si3402 Rev. 1.31 11 3.2.1. Rectification Diode Bridges and Surge Suppressor The 802.3 specification defines the input voltage at the RJ-45 connector of the PD with no reference to polarity. In other words, the PD must be able to accept power of either polarity at each of its inputs. This requirement necessitates the use of two sets of diode bridges, one for the CT1 and CT2 pins and one for the SP1 and SP2 pins to rectify the voltage. Furthermore, the standard requires that a PD withstand a high-voltage transient surge consisting of a 1000 V common-mode impulse with 300 ns rise time and 50 µs half fall time. Typically, the diode bridge and the surge suppressor have been implemented externally, adding cost and complexity to the PD system design. The diode bridge* and the surge suppressor have been integrated into the Si3402, thus reducing system cost and design complexity. *Note: Silicon Laboratories recommends that on-chip diode bridges be bypassed when >7 W of output power is required. By integrating the diode bridges, the Si3402 gains access to the input side of the diode bridge. Monitoring the voltage at the input of the diode bridges instead of the voltage across the load capacitor provides the earliest indication of a power loss. This true early power loss indicator, PLOSS, provides a local microcontroller time to save states and shut down gracefully before the load capacitor discharges below the minimum 802.3- specified operating voltage of 36 V. Integration of the surge suppressor enables optimization of the clamping voltage and guarantees protection of all connected circuitry. As an added benefit, the transient surge suppressor, when tripped, actively disables the hotswap interface and switching regulator, preventing downstream circuits from encountering the high-energy transients. 3.2.2. Detection In order to identify a device as a valid PD, a PSE will apply a voltage in the range of 2.8 to 10 V on the cable and look for the 25.5 k signature resistor. The Si3402 will react to voltages in this range by connecting an external 25.5 k resistor between VPOS and VNEG. This external resistor and internal low-leakage control circuitry create the proper signature to alert the PSE that a valid PD has been detected and is ready to have power applied. The internal hotswap switch is disabled during this time to prevent the switching regulator and attached load circuitry from generating errors in the detection signature. Since the Si3402 integrates the diode bridges, the IC can compensate for the voltage and resistance effects of the diode bridges. The 802.3 specification requires that the PSE use a multi-point, V/I measurement technique to remove the diode-induced dc offset from the signature resistance measurement. However, the specification does not address the diode's nonlinear resistance and the error induced in the signature resistor measurement. Since the diode's resistance appears in series with the signature resistor, the PD system must find some way of compensating for this error. In systems where the diode bridges are external, compensation is difficult and suffers from errors. Since the diode bridges are integrated in the Si3402, the IC can compensate for this error by offsetting resistance across all operating conditions and thus meeting the 802.3 requirements. An added benefit is that this function can be tested during the IC’s automated testing step, guaranteeing system compliance when used in the final PD application. For more information about supporting higher-power applications (above 12.95 W), see “AN313: Using the Si3402 in High Power Applications” and “AN314: Power Combining Circuit for PoE for up to 18.5 W Output”. 3.2.3. Classification Once the PSE has detected a valid PD, the PSE may classify the PD for one of five power levels or classes. A class is based on the expected power consumption of the powered device. An external resistor sets the nominal class current that can then be read by the PSE to determine the proper power requirements of the PD. When the PSE presents a fixed voltage between 15.5 V and 20.5 V to the PD, the Si3402 asserts the class current from VPOS through the RCL resistor. The resistor values associated with each class are shown in Table 10. Table 9. Hotswap Interface Modes Input Voltage (|CT1-CT2| or |SP1-SP2|) Si3402 Mode 0 to 2.7 V Inactive 2.7 to 11 V Detection signature 11 to 14 V Detection turns off and internal bias starts 14 to 22 V Classification signature 22 to 42 V Transition region 42 up to 57 V Switcher operating mode (hysteresis limit based on rising input voltage) 57 down to 36 V Switcher operating mode (hysteresis limit based on falling input voltage) |
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