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MA31751 Datasheet(PDF) 4 Page - Dynex Semiconductor |
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MA31751 Datasheet(HTML) 4 Page - Dynex Semiconductor |
4 / 17 page MA31751 4/17 AS[0:3] A[0:15] EA[3:10] A[4:15] PB[0:3] AS[0:3] A[0:15] EA[0:10] A[4:15] 1750A Addressing Logical Physical 1750B Addressing Logical* Physical 1750A Extended Physical Address [0:19] 1750B Extended Physical Address [0:22] EA3 A4 A15 AS0 AS3 A0 PA0 PA19 EA10 A15 PA0 PA22 A15 A4 EA10 EA0 PB0 PB3 AS3 AS0 A15 A0 * There are 16M words of logical address in 1750B. The 16MWord logical to 8MWord physical mapping is user defined. Figure 4: Extended Address Mapping in 1750A/B Mode Figure 5: MA31751 Selection Chart for Varying Memory Requirements Addressable Physical Memory Addressable Logical Memory Is BPU Protection Required? Mode Number of MMUs Number of BPUs Number of MA31751s Required 64KW 64KW NO A 0 0 0 1MW 1MW NO A 1 0 1 64KW 64KW YES A 0 1 1 1MW 1MW YES A 1 1 1 64KW 64KW NO B 0 0 0 8MW 1MW NO B 1 0 1 8MW 2MW NO B 2 0 2 8MW 4MW NO B 4 0 4 8MW 8MW NO B 8 0 8 8MW 16MW NO B 16 0 16 64KW 64KW YES B 0 1 1 8MW 1MW YES B 1 8 8 8MW 2MW YES B 2 8 8 8MW 4MW YES B 4 8 8 8MW 8MW YES B 8 8 8 8MW 16MW YES B 16 8 16 Notes: 1. Memory is specified in terms of addressable instruction space. 2. It is assumed that the whole of the physical address space is used in 1750B - if this is not the case the number of MA31751 chips may be reduced. |
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