EPM3032A datasheet(5/46 Pages) ALTERA

Part #	EPM3032A

Description	Programmable Logic Device Family

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Manufacturer	ALTERA [Altera Corporation]

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Altera Corporation

5

MAX 3000A Programmable Logic Device Family Data Sheet

Figure 1. MAX 3000A Device Block Diagram

Note:

(1)

EPM3032A, EPM3064A, EPM3128A, and EPM3256A devices have six output enables. EPM3512A devices have

10 output enables.

Logic Array Blocks

The MAX 3000A device architecture is based on the linking of

high–performance LABs. LABs consist of 16–macrocell arrays, as shown

in Figure 1. Multiple LABs are linked together via the PIA, a global bus

that is fed by all dedicated input pins, I/O pins, and macrocells.

Each LAB is fed by the following signals:

■

36 signals from the PIA that are used for general logic inputs

■

Global controls that are used for secondary register functions

6 or 10

INPUT/GCLRn

6 or 10 Output Enables (1)

16

36

16

I/O

Control

Block

LAB C

LAB D

I/O

Control

Block

6 or 10

16

36

16

I/O

Control

Block

LAB A

Macrocells

1 to 16

LAB B

I/O

Control

Block

6 or 10

PIA

INPUT/GCLK1

INPUT/OE2/GCLK2

INPUT/OE1

2 to 16 I/O

2 to

16

2 to

16

2 to

16

2 to

16

2 to 16

Macrocells

17 to 32

Macrocells

33 to 48

Macrocells

49 to 64

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