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C8051F102 Datasheet(PDF) 11 Page - Silicon Laboratories |
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C8051F102 Datasheet(HTML) 11 Page - Silicon Laboratories |
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11 / 350 page  C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Rev. 1.4 11 13. Reset Sources Figure 13.1. Reset Sources.................................................................................... 177 Figure 13.2. Reset Timing ...................................................................................... 178 14. Oscillators Figure 14.1. Oscillator Diagram.............................................................................. 185 Figure 14.2. PLL Block Diagram............................................................................. 191 15. Flash Memory Figure 15.1. Flash Memory Map for MOVC Read and MOVX Write Operations ... 201 Figure 15.2. 128 kB Flash Memory Map and Security Bytes ................................. 204 Figure 15.3. 64 kB Flash Memory Map and Security Bytes ................................... 205 16. Branch Target Cache Figure 16.1. Branch Target Cache Data Flow ........................................................ 211 Figure 16.2. Branch Target Cache Organiztion...................................................... 212 Figure 16.3. Cache Lock Operation........................................................................ 214 17. External Data Memory Interface and On-Chip XRAM Figure 17.1. Multiplexed Configuration Example.................................................... 222 Figure 17.2. Non-multiplexed Configuration Example ............................................ 223 Figure 17.3. EMIF Operating Modes ...................................................................... 224 Figure 17.4. Non-multiplexed 16-bit MOVX Timing ................................................ 227 Figure 17.5. Non-multiplexed 8-bit MOVX without Bank Select Timing ................. 228 Figure 17.6. Non-multiplexed 8-bit MOVX with Bank Select Timing ...................... 229 Figure 17.7. Multiplexed 16-bit MOVX Timing........................................................ 230 Figure 17.8. Multiplexed 8-bit MOVX without Bank Select Timing ......................... 231 Figure 17.9. Multiplexed 8-bit MOVX with Bank Select Timing .............................. 232 18. Port Input/Output Figure 18.1. Port I/O Cell Block Diagram ............................................................... 235 Figure 18.2. Port I/O Functional Block Diagram ..................................................... 237 Figure 18.3. Priority Crossbar Decode Table (EMIFLE = 0; P1MDIN = 0xFF)....... 238 Figure 18.4. Priority Crossbar Decode Table (EMIFLE = 1; EMIF in Multiplexed Mode; P1MDIN = 0xFF) ................ 241 Figure 18.5. Priority Crossbar Decode Table (EMIFLE = 1; EMIF in Non-Multiplexed Mode; P1MDIN = 0xFF) ........ 242 Figure 18.6. Crossbar Example.............................................................................. 244 19. System Management Bus / I2C Bus (SMBus0) Figure 19.1. SMBus0 Block Diagram ..................................................................... 259 Figure 19.2. Typical SMBus Configuration ............................................................. 260 Figure 19.3. SMBus Transaction ............................................................................ 261 Figure 19.4. Typical Master Transmitter Sequence................................................ 262 Figure 19.5. Typical Master Receiver Sequence.................................................... 262 Figure 19.6. Typical Slave Transmitter Sequence.................................................. 263 Figure 19.7. Typical Slave Receiver Sequence...................................................... 263 20. Enhanced Serial Peripheral Interface (SPI0) Figure 20.1. SPI Block Diagram ............................................................................. 273 Figure 20.2. Multiple-Master Mode Connection Diagram ....................................... 276 Figure 20.3. 3-Wire Single Master and Slave Mode Connection Diagram ............. 276 |
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