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DCR504ST11 Datasheet(PDF) 6 Page - Dynex Semiconductor |
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DCR504ST11 Datasheet(HTML) 6 Page - Dynex Semiconductor |
6 / 8 page 6/8 www.dynexsemi.com DCR504ST Fig.6 Maximum (limit) transient thermal impedance - junction to case Fig.7 Surge (non-repetitive) on-state current vs time (with 50% V RRM at T case 125˚C) 10 1 0.1 0.01 0.001 Time - (s) 1.0 0.1 0.01 0.001 Double side cooled Anode side cooled Conduction d.c. Halfwave 3 phase 120˚ 6 phase 60˚ Effective thermal resistance Junction to case ˚C/W Double side 0.063 0.073 0.093 0.112 Anode side 0.11 0.12 0.14 0.16 20 15 10 5 0 110 1 2 3 45 50 ms Cycles at 50Hz Duration 50 100 I2t I2t = Î2 x t 2 150 10 20 30 Fig.4 Recovered charge Fig.5 Gate characteristics 10 1 0.1 0.01 0.001 Gate trigger current, IGT - (A) 100 10 1 0.1 Region of certain triggering Upper limit 95% Lower limit 5% VGD IFGM 0.1 1.0 10 100 Rate of decay of on-state current, dIT/dt - (A/µs) 10000 1000 100 Conditions: Tj = 125˚C VR = 50V tp = 1ms IT = 300A 0.25xIRM IRM QR tp IT dIT/dt |
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