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EPM7128A Datasheet(PDF) 2 Page - Altera Corporation |
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EPM7128A Datasheet(HTML) 2 Page - Altera Corporation |
2 / 64 page 2 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet ...and More Features ■ 4.5-ns pin-to-pin logic delays with counter frequencies of up to 227.3 MHz ■ MultiVoltTM I/O interface enables device core to run at 3.3 V, while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels ■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), space- saving FineLine BGATM, and plastic J-lead chip carrier (PLCC) packages ■ Supports hot-socketing in MAX 7000AE devices ■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance ■ PCI-compatible ■ Bus-friendly architecture, including programmable slew-rate control ■ Open-drain output option ■ Programmable macrocell registers with individual clear, preset, clock, and clock enable controls ■ Programmable power-up states for macrocell registers in MAX 7000AE devices ■ Programmable power-saving mode for 50% or greater power reduction in each macrocell ■ Configurable expander product-term distribution, allowing up to 32 product terms per macrocell ■ Programmable security bit for protection of proprietary designs ■ 6 to 10 pin- or logic-driven output enable signals ■ Two global clock signals with optional inversion ■ Enhanced interconnect resources for improved routability ■ Fast input setup times provided by a dedicated path from I/O pin to macrocell registers ■ Programmable output slew-rate control ■ Programmable ground pins Table 1. MAX 7000A Device Features Feature EPM7032AE EPM7064AE EPM7128AE EPM7256AE EPM7512AE Usable gates 600 1,250 2,500 5,000 10,000 Macrocells 32 64 128 256 512 Logic array blocks 2 4 8 16 32 Maximum user I/O pins 36 68 100 164 212 tPD (ns) 4.5 4.5 5.0 5.5 7.5 tSU (ns) 2.9 2.8 3.3 3.9 5.6 tFSU (ns) 2.5 2.5 2.5 2.5 3.0 tCO1 (ns) 3.0 3.1 3.4 3.5 4.7 fCNT (MHz) 227.3 222.2 192.3 172.4 116.3 |
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