EN5364QI

Pin Descriptions

PIN

NAME

FUNCTION

1-4,

27-33,

64-68

PGND

Input/Output power ground. Connect these pins to the ground electrode of the input

and output filter capacitors. See VOUT and PVIN descriptions for more details.

5-13

VOUT

Regulated converter output. Connect to the load, and place output filter capacitor(s)

between these pins and PGND pins 1-4 and 64-68.

14-24,

44-47

NC

NO CONNECT: These pins must be soldered to PCB but not be electrically connected

to each other or to any external signal, voltage, or ground. These pins may be

connected internally. Failure to follow this guideline may result in device damage.

25-26

NC(SW)

NO CONNECT: These pins are internally connected to the common switching node of

the internal MOSFETs. They must be soldered to PCB but not be electrically

connected to any external signal, ground, or voltage. Failure to follow this guideline

may result in device damage.

34-43

PVIN

Input power supply. Connect to input power supply, place input filter capacitor(s)

between these pins and PGND pins 27-33.

48

S_OUT

Clock Output. Depending on the mode, either a clock signal or the PWM signal is

output on this pin. These signals are delayed by a time that is related to the resistor

connected between S_DELAY and AGND. Leave this pin floating if not needed.

49

S_IN

Clock Input. Depending on the mode, this pin accepts either an input clock to

synchronize the internal switching frequency or the S_OUT signal from another

EN5364QI. Leave this pin floating if it is not used.

50

M/S

This is a Ternary Input. Floating the pin disables parallel operation. A low level

configures the device as Master and a High level configures the device as a slave.

51

EN_PB

This is the Enable Pre-Bias Input. When this pin is pulled high, the Device will support

monotonic start-up under a pre-biased load. There is a 150k

Ω pull-down on this pin.

52

ENABLE

This is the Device Enable pin. A high level enables the device while a low level

disables the device.

53

AVIN

54

POK

Power OK is an open drain transistor for power system state indication. POK is a

logic high when VOUT is with -10% to +20% of VOUT nominal. Being an open drain

output allows several devices to be wired to logically AND the function. Size pull-up

resistor to limit current to 4mA when POK is low.

55

AGND

Ground return for the controller. Needs to be connected to a quiet ground.

56

VFB

External Feedback input. The feedback loop is closed through this pin. A voltage

connected to VFB. The control loop regulates to make the VFB node voltage 0.6V.

57

EAOUT

Optional Error Amplifier output. Allows for customization of the control loop.

58

OCP_ADJ

When this pin is pulled to AGND, the overcurrent protection trip point is increased by

approximately 30%. Leave floating for default OCP threshold (see Electrical

Characteristics table). Tie this pin to AGND for pin compatibility with the EN5394.

59

SS

A soft-start capacitor is connected between this pin to AGND. The value of the

capacitor controls the soft-start interval and startup time.

60

S_DELAY

A resistor is connected between this pin and AGND. The value of the resistor controls

the delay in S_OUT. This pin can be left floating if the S_OUT function is not used.

61-62

MAR1,

MAR2

These are 2 ternary input pins. Each pin can be a logical Lo, Logical Hi or Float

condition. 7 of the 9 states are used to modulate the output voltage by 0%, ±2.5%,

±5% or ±10%. The 8th state is used to by-pass the delay in S_OUT. See Functional

Description section.

63

VSENSE

This pin senses VOUT when the device is placed in the Back-feed (or Pre-bias) mode.

69, 70

PGND

Device thermal pads to be connected to the system gnd plane. See Layout

Recommendations section.

3

www.altera.com/enpirion

03544

October 11, 2013

Rev E