 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
C8051T631-GM Datasheet(PDF) 8 Page - Silicon Laboratories |
|
||||||||||||||||||||||||||||||
C8051T631-GM Datasheet(HTML) 8 Page - Silicon Laboratories |
|
|
8 / 221 page  C8051T630/1/2/3/4/5 8 Rev. 1.0 Figure 20.4. Crossbar Priority Decoder with Crystal Pins Skipped ....................... 115 21. SMBus Figure 21.1. SMBus Block Diagram ...................................................................... 127 Figure 21.2. Typical SMBus Configuration ............................................................ 128 Figure 21.3. SMBus Transaction ........................................................................... 129 Figure 21.4. Typical SMBus SCL Generation ........................................................ 131 Figure 21.5. Typical Master Write Sequence ........................................................ 140 Figure 21.6. Typical Master Read Sequence ........................................................ 141 Figure 21.7. Typical Slave Write Sequence .......................................................... 142 Figure 21.8. Typical Slave Read Sequence .......................................................... 143 22. UART0 Figure 22.1. UART0 Block Diagram ...................................................................... 148 Figure 22.2. UART0 Baud Rate Logic ................................................................... 149 Figure 22.3. UART Interconnect Diagram ............................................................. 150 Figure 22.4. 8-Bit UART Timing Diagram .............................................................. 150 Figure 22.5. 9-Bit UART Timing Diagram .............................................................. 151 Figure 22.6. UART Multi-Processor Mode Interconnect Diagram ......................... 152 23. Enhanced Serial Peripheral Interface (SPI0) Figure 23.1. SPI Block Diagram ............................................................................ 156 Figure 23.2. Multiple-Master Mode Connection Diagram ...................................... 158 Figure 23.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram .......................................... 159 Figure 23.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram ................................... 159 Figure 23.5. Master Mode Data/Clock Timing ....................................................... 161 Figure 23.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 161 Figure 23.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 162 Figure 23.8. SPI Master Timing (CKPHA = 0) ....................................................... 166 Figure 23.9. SPI Master Timing (CKPHA = 1) ....................................................... 166 Figure 23.10. SPI Slave Timing (CKPHA = 0) ....................................................... 167 Figure 23.11. SPI Slave Timing (CKPHA = 1) ....................................................... 167 24. Timers Figure 24.1. T0 Mode 0 Block Diagram ................................................................. 172 Figure 24.2. T0 Mode 2 Block Diagram ................................................................. 173 Figure 24.3. T0 Mode 3 Block Diagram ................................................................. 174 Figure 24.4. Timer 2 16-Bit Mode Block Diagram ................................................. 179 Figure 24.5. Timer 2 8-Bit Mode Block Diagram ................................................... 180 Figure 24.6. Timer 2 Low-Frequency Oscillation Capture Mode Block Diagram ... 181 Figure 24.7. Timer 3 16-Bit Mode Block Diagram ................................................. 185 Figure 24.8. Timer 3 8-Bit Mode Block Diagram ................................................... 186 Figure 24.9. Timer 3 Low-Frequency Oscillation Capture Mode Block Diagram ... 187 25. Programmable Counter Array Figure 25.1. PCA Block Diagram ........................................................................... 191 Figure 25.2. PCA Counter/Timer Block Diagram ................................................... 192 Figure 25.3. PCA Interrupt Block Diagram ............................................................ 193 |
Similar Part No. - C8051T631-GM |
|
Similar Description - C8051T631-GM |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
