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MAX5815AAUD+T Datasheet(PDF) 7 Page - Maxim Integrated Products |
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MAX5815AAUD+T Datasheet(HTML) 7 Page - Maxim Integrated Products |
7 / 30 page MAX5813/MAX5814/MAX5815 Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface 7 Maxim Integrated Note 3: Electrical specifications are production tested at TA = +25°C. Specifications over the entire operating temperature range are guaranteed by design and characterization. Typical specifications are at TA = +25°C and are not guaranteed. Note 4: DC Performance is tested without load. Note 5: Linearity is tested with unloaded outputs to within 20mV of GND and VDD. Note 6: Offset and gain errors are calculated from measurements made with VREF = VDD at code 30 and 4065 for MAX5815, code 8 and 1016 for MAX5814, and code 2 and 254 for MAX5813. Note 7: Subject to zero and full-scale error limits and VREF settings. Note 8: Measured with all other DAC outputs at midscale with one channel transitioning 0 to full scale. Note 9: On power-up, the device initiates an internal 200µs (typ) calibration sequence. All commands issued during this time will be ignored. Note 10: Guaranteed by design. Note 11: All channels active at VFS, unloaded. Static logic inputs with VIL = VGND and VIH = VDDIO. Note 12: An unconnected condition on the ADDR_ pins is sensed via a resistive pullup and pulldown operation; for proper operation, ADDR_ pins should be tied to VDDIO, GND, or left unconnected with minimal capacitance. Typical Operating Characteristics (MAX5815, 12-bit performance, TA = +25°C, unless otherwise noted.) Figure 1. I2C Serial Interface Timing Diagram ELECTRICAL CHARACTERISTICS (continued) (VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) INL vs. CODE CODE (LSB) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 VDD = VREF = 3V NO LOAD INL vs. CODE CODE (LSB) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 VDD = VREF = 5V NO LOAD DNL vs. CODE CODE (LSB) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 VDD = VREF = 3V NO LOAD tSU;STO tr tSP tHD;STA tSU;STA tf tHIGH tHD;DAT tLOW tCLPW tCLRSTA tLDH tLDPW tHD;STA tf S S Sr P SDA SCL CLR LDAC tSU;DAT tr tBUF |
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