ICS527-01

CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER

ZDB AND MULTIPLIER/DIVIDER

IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 5

ICS527-01

REV G 051310

Typical Example

The following connection diagram shows the implementation of the example from the previous section.

This will generate a 50 MHz clock synchronously with a 40 MHz input. A SYNC pulse is desired and the 1x

output drive is selected.T

Note: The series termination resistor is located before the feedback trace.

This will give the following waveforms:

Multiple Output Example

In this example, an input clock of 125 MHz is used. Eight copies of 50 MHz are required as are eight copies

of 25 MHz, de-skewed and aligned to the 125 MHz input clock. The following solution uses the

MK74CB218 which has dual 1 to 8 buffers with low pin-to-pin skew.

F6

ICLK

F5

F4

GND

F3

OECLK2

2XDRIVE

F0

F1

F2

CLK1

CLK2

GND

S1

VDD

R0

VDD

DIV2

S0

R2

R1

R5

R6

R4

R3

FBIN

PDTS

50 MHz

SYNC

33

33

0.01 F

40 MHz

0.01 F

VDD

40 MHz

ICLK

50 MHz

CLK1

SYNC

CLK2