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527R-01LFT Datasheet(PDF) 6 Page - Integrated Device Technology |
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527R-01LFT Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 11 page ICS527-01 CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER ZDB AND MULTIPLIER/DIVIDER IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 6 ICS527-01 REV G 051310 Using the equation for selecting dividers gives: If FDW = 0, then RDW = 8. This gives the required divide-by-5 function. Setting pin DIV2 = 1 gives both a 25 MHz and a 50 MHz output from the ICS527-01. The FBIN pin is connected to the QA7 output of the MK74CB218. This aligns all the outputs of the MK74CB218 with the 25 MHz input since the ICS527-01 aligns rising edges on the ICLK and FBIN pins. The propagation delay of the buffer is compensated by the PLL. In this example, series termination resistors have been omitted for clarity but should be used on all clock outputs. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No via’s should be used 125 MHz, ICLK 25 MHz, QA0-7 50 MHz, QB0-7 F6 ICLK F5 F4 GND F3 OECLK2 2XDRIVE F0 F1 F2 CLK1 CLK2 GND S1 VDD R0 VDD DIV2 S0 R2 R1 R5 R6 R4 R3 FBIN PDTS 0.01 F 125 MHz 25 MHz 0.01 F VDD QB5 QA3 QB6 QB7 VDD GND QA5 QA6 QA7 OE QB3 QB4 GND VDD VDD VDD VDD QA1 QA2 QB1 QB2 INA QA0 INB QB0 QA4 GND GND 0.01 F 0.01 F The layout design above produces the waveforms shown below. Note: Series terminating resistors are not shown. 0.01 F (FDW + 2) (RDW + 2) 25 MHz = 125 MHz x |
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