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LNK6767EVK Datasheet(PDF) 10 Page - Power Integrations, Inc. |
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LNK6767EVK Datasheet(HTML) 10 Page - Power Integrations, Inc. |
10 / 24 page Rev. C 03/14 10 LinkSwitch-HP www.powerint.com www.powerint.com Layout Considerations for eSIP-7C Package Figure 12 is the layout for a 30 W adapter shown in the schematic Figure 11. An eSIP-7C package is used as indicated by the suffix in LNK6766E which allows the use of a stand-up heat sink. The mounting pin for the heat sink should be electrically isolated. It can be seen that the primary return trace wraps around the LinkSwitch-HP device which acts as a shield around the critical external control related components of LinkSwitch-HP. These components include R7, R8, R19, R20 and C5, C8, C20. Of particular importance is placing the bypass capacitor C5 and COMPENSATION pin noise filter capacitor C8 as close as possible to SOURCE pin with very short trace lengths to COMPENSATION and BYPASS pins as shown. If an electrolytic capacitor is selected as the bypass capacitor (C5) then an additional 100 nF (C5) ceramic must also be fitted. The ground trace wrap, tight layout and single point grounding to SOURCE pin of these components avoids having noise related issues during peak loads or during line transient such as surge or ESD events. Another consideration for ESD and line surge is the primary- side termination of the Y capacitor. The Y capacitor C18 should be tied to the positive terminal of the bulk capacitor C2 in order to route the potential of high currents away from the more sensitive primary return traces. Because of the tight layout common to adapter applications, this design uses triple insulated wire and flying leads for output winding termination to avoid secondary arcing to core during ESD events. The trace connecting the drain to transformer should be very short and the primary clamp circuitry should be grouped together and away from the more sensitive components. The bias winding return and return of bias capacitor C6 should be routed separately to the negative terminal of the input capacitor C2 away from SOURCE pin. The secondary rectifying loop that includes the secondary winding, the output diode D8, and the first output capacitor C13 should be as tight as possible to minimize adding series inductance which can reduce high load efficiency and degrade the quality of regulation. Figure 12. Layout for 30 W Adapter Using a eSIP-7C Package (View From Bottom Copper Layer). |
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