DS80C390-FCR datasheet(4/58 Pages) DALLAS

Part #	DS80C390-FCR

Description	Dual CAN High-Speed Microprocessor

Download	58 Pages

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Manufacturer	DALLAS [Dallas Semiconductor]

Direct Link	https://www.maximintegrated.com/en.html

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DS80C390

4 of 58

110199

PIN DESCRIPTION Table 1

LQFP

PLCC

SIGNAL

NAME

DESCRIPTION

8, 22,

40, 56

17, 32,

51, 68

VCC

+5V

9, 25,

41, 57

1, 18,

35, 52

GND

Digital Circuit Ground

46

57

ALE

Address Latch Enable - Output. When the MUX pin is low, this

pin outputs a clock to latch the external address LSB from the

multiplexed address/data bus on Port 0. This signal is commonly

connected to the latch enable of an external transparent latch. ALE

has a pulse width of 1.5 XTAL1 cycles and a period of four

XTAL1 cycles. When the MUX pin is high, the pin will toggle

continuously if the ALEOFF bit is cleared.

ALE is forced high

when the device is in a Reset condition or if the ALEOFF bit is set

while the MUX pin is high.

45

56

PSEN

Program Store Enable - Output. This signal is the chip enable for

external ROM memory. PSEN provides an active low pulse and is

driven high when external ROM is not being accessed.

47

58

EA

External Access Enable - Input. This pin must be tied to GND for

proper operation.

26

36

MUX

Multiplex/Demultiplex Select - Input.

This pin selects if the

address/data

bus

operates

in

multiplexed

( MUX =0)

or

demultiplexed ( MUX =1) mode.

2

11

RST

Reset - Input. The RST input pin contains a Schmitt voltage input

to recognize external active high Reset inputs.

The pin also

employs an internal pulldown resistor to allow for a combination of

wired OR external Reset sources. An RC circuit is not required for

power-up, as the device provides this function internally.

3

12

RSTOL

Reset Output Low- Output. This active low signal will be

asserted:

When the processor has entered reset via the RST pin,

During crystal warm-up period following power-on or Stop mode,

During a watchdog timer reset (2 cycles duration),

During an oscillator failure (if OFDE=1),

Whenever VCC

≤ V

RST

23,

24

33,

34

XTAL2,

XTAL1

XTAL1, XTAL2 - Crystal oscillator pins support fundamental

mode, parallel resonant, AT cut crystals. XTAL1 is the input if an

external clock source is used in place of a crystal. XTAL2 is the

output of the crystal amplifier.

55

54

53

52

51

50

49

48

67

66

65

64

63

62

61

59

AD0 / D0

AD1 / D1

AD2 / D2

AD3 / D3

AD4 / D4

AD5 / D5

AD6 / D6

AD7 / D7

AD0-7 (Port 0) - I/O. When the MUX pin is tied low, Port 0 is the

multiplexed address/data bus. While ALE is high, the LSB of a

memory address is presented. While ALE falls, the port transitions

to a bi-directional data bus. When the MUX pin is tied high, Port 0

functions as the bi-directional data bus. Port 0 cannot be modified

by software. The reset condition of Port 0 pins is high. No pullup

resistors are needed.

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DS80C390-FCR Datasheet(PDF) 4 Page - Dallas Semiconductor

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