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DS5002FP Datasheet(PDF) 4 Page - Dallas Semiconductor |
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DS5002FP Datasheet(HTML) 4 Page - Dallas Semiconductor |
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4 / 25 page  DS5002FP Secure Microprocessor Chip 4 of 25 AC CHARACTERISTICS—EXPANDED BUS MODE TIMING SPECIFICATIONS (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 1 and Figure 2) # PARAMETER SYMBOL CONDITIONS MIN MAX UNITS 1 Oscillator Frequency 1 / tCLK 1.0 16 MHz 2 ALE Pulse Width tALPW 2tCLK - 40 ns 3 Address Valid to ALE Low tAVALL tCLK - 40 ns 4 Address Hold After ALE Low tAVAAV tCLK - 35 ns 14 RD Pulse Width tRDPW 6tCLK - 100 ns 15 WR Pulse Width tWRPW 6tCLK - 100 ns 12MHz 5tCLK - 165 16 RD Low to Valid Data In tRDLDV 16MHz 5tCLK - 105 ns 17 Data Hold after RD High tRDHDV 0 ns 18 Data Float after RD High tRDHDZ 2tCLK - 70 ns 12MHz 8tCLK - 150 19 ALE Low to Valid Data In tALLVD 16MHz 8tCLK - 90 ns 12MHz 9tCLK - 165 20 Valid Address to Valid Data In tAVDV 16MHz 9tCLK - 105 ns 21 ALE Low to RD or WR Low tALLRDL 3tCLK - 50 3tCLK + 50 ns 22 Address Valid to RD or WR Low tAVRDL 4tCLK - 130 ns 23 Data Valid to WR Going Low tDVWRL tCLK - 60 ns 12MHz 7tCLK - 150 24 Data Valid to WR High tDVWRH 16MHz 7tCLK - 90 ns 25 Data Valid after WR High tWRHDV tCLK-50 ns 26 RD Low to Address Float tRDLAZ 0 ns 27 RD or WR High to ALE High tRDHALH tCLK - 40 tCLK + 50 ns Figure 1. Expanded Data Memory Read Cycle |
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