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DS2480S Datasheet(PDF) 2 Page - Dallas Semiconductor |
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DS2480S Datasheet(HTML) 2 Page - Dallas Semiconductor |
2 / 26 page DS2480 042498 2/26 DETAILED PIN DESCRIPTION PIN SYMBOL DESCRIPTION 1 GND Ground Pin: common ground reference and ground return for 1–Wire bus 2 1–W 1–Wire Input/Output Pin: 1–Wire bus with slew–rate–controlled pull–down, active pull–up, ability to switch in VPP to program EPROM, and ability to switch in VDD through a low–impedance path to program EEPROM, perform a temper- ature conversion or operate the Crypto iButton. 3 NC No Connection Pin. 4 VDD Power Input Pin: power supply for the chip and 1–Wire pull–up voltage. 5V ± 10%; may be derived from 12V VPP with an external voltage regulator. 5 VPP EPROM Programming Voltage: 12V supply input for EPROM programming; if EPROM programming is not required, this pin must be tied to VDD. VPP must come up before VDD. 6 POL RXD/TXD Polarity Select: RXD/TXD polarity select; tied to GND for RS232 (12V or 5V) connection, tied to VDD for direct connection to UART chip. 7 TXD Serial Data from UART: data input from host (inverted or true); maximum volt- age swing –0.3V to VDD + 0.3V; for logic thresholds see DC specifications. 8 RXD Serial Data to UART: signal output to host; push–pull driver with CMOS com- patible levels; for true ±12V RS232 systems an external level–translator must be provided. OVERVIEW The DS2480 directly interfaces a 5V serial communica- tion port with its lines TXD (transmit) and RXD (receive) to a 1–Wire bus. In addition the device performs a speed conversion allowing the data rate at the communication port to be different from the 1–Wire date rate. Several parameters relating to the 1–Wire port and its timing as well as the communication speed at both the port and the 1–Wire bus are configurable. The circuit to achieve these functions is outlined in Figure 1, Block Diagram. The device gets its input data from the serial commu- nication port of the host computer through pin TXD. For compatibility with active–high as well as active–low sys- tems, the incoming signal can be inverted by means of the polarity input POL. The polarity chosen by hard–wir- ing the logic level of this pin is also valid for the output pin RXD. If for minimizing the interface hardware an asym- metry between RXD and TXD is desired, this can be achieved by setting the most significant bit of the Speed Control parameter to a 1 (see Configuration Parameter Value Codes). With the MS bit of the speed control set to 1, the polarity at TXD is still selected by the logic level at POL, but the polarity at RXD will be the opposite of what the logic level at POL specifies. As data enters the core of the DS2480’s logic circuitry, it is analyzed to separate data and command bytes and to calibrate the device’s timing generator. The timing gen- erator controls all speed relations of the communication interface and the 1–Wire bus as well as the wave forms on the 1–Wire bus. Command bytes either affect the configuration setting or generate certain wave forms on the 1–Wire bus. Data bytes are simply translated by the protocol converter into the appropriate 1–Wire activities. Each data byte generates a return byte from the 1–Wire bus, that is communicated back to the host through the RXD pin as soon as the activity on the 1–Wire bus is completed. The 1–Wire driver shapes the slopes of the 1–Wire wave forms, applies programming pulses or strong pull–up to 5 volts and reads the 1–Wire bus using a non– TTL threshold to maximize the noise margin for best performance on large 1–Wire MicroLAN networks. |
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