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PE4280 Datasheet(PDF) 3 Page - Peregrine Semiconductor |
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PE4280 Datasheet(HTML) 3 Page - Peregrine Semiconductor |
3 / 8 page Product Specification PE4280 Page 3 of 8 ©2010-11 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0164-05 │ www.psemi.com Table 5. RF Path Truth Table Table 6. Termination Truth Table Notes: 1. The operation of the PE4280 is not supported or characterized in the C1 = VDD and C2 = VDD state. 2. "X" denotes termination enabled. C1 C2 RFC – RF1 RFC – RF2 Low Low OFF OFF Low High OFF ON High Low ON OFF High High N/A1 N/A1 C1 C2 RFC – 75 Ω RF1 – 75 Ω RF2 – 75 Ω Low Low X2 X2 X2 Low High X2 High Low X2 High High N/A1 N/A1 N/A1 Switching Frequency The PE4280 has a maximum 25 kHz switching rate when the internal negative voltage generator is used (pin 18 = GND). The rate at which the PE4280 can be switched is only limited to the switching time if an external -3 V supply is provided at pin 18 (VSS). Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com |
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