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DS2176 Datasheet(PDF) 8 Page - Dallas Semiconductor |
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DS2176 Datasheet(HTML) 8 Page - Dallas Semiconductor |
8 / 15 page DS2176 8 of 15 SIGNALING SUPERVISION MODES Table 2 SM0 SM1 FMS SELECTED MODE 0 0 0 193S framing, no integration, 1 multiframe freeze. 0 0 1 193E framing, no integration, 1 multiframe freeze. 0 1 0 193S framing, 2 multiframes integration and freeze. 0 1 1 193E framing, 2 multiframes integration and freeze. 1 0 0 1 193S framing, 5 multiframes integration, 2 multiframes freeze. 1 0 1 1 193E framing, 3 multiframes integration, 2 multiframes freeze. 1 1 0 193S framing, no integration, 1 multiframe freeze, replace robbed bit signaling bits at SSER with ones. 1 1 1 193E framing, no integration, 1 multiframe freeze, replace robbed bit signaling bits at SSER with ones. NOTE: 1. During slip or alarm conditions, integration is limited to two multiframes to minimize signaling delay. SLIP AND SIGNALING SUPERVISION LOGIC TIMING Figure 7 NOTES: 1. Integration feature disabled (SM0=SM1=0) in timing set shown. 2. Depending on present buffer depth, forcing ALN low may or may not cause a slip condition. |
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