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DS1742-100 Datasheet(PDF) 4 Page - Dallas Semiconductor |
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DS1742-100 Datasheet(HTML) 4 Page - Dallas Semiconductor |
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4 / 12 page  DS1742 4 of 12 address inputs are changed while CE , and OE remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate until the next address access. WRITING DATA TO RAM OR CLOCK The DS1742 is in the write mode whenever WE , and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE , on CE . The addresses must be held valid throughout the cycle. CE , or WE must return inactive for a minimum of tWR prior to the initiation of another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the data bus can become active with read data defined by the address inputs. A low transition on WE will then disable the outputs tWEZ after WE goes active. DATA RETENTION MODE The 5-volt device is fully accessible and data can be written or read only when VCC is greater than VPF. However, when VCC is below the power fail point, VPF, (point at which write protection occurs) the internal clock registers and SRAM are blocked from any access. At this time the power fail reset output signal ( RST ) is driven active and will remain active until VCC returns to nominal levels. When VCC falls below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. The 3.3 volt device is fully accessible and data can be written or read only when VCC is greater than VPF. When VCC falls below the power fail point, VPF, access to the device is inhibited. At this time the power fail reset output signal ( RST ) is driven active and will remain active until VCC returns to nominal levels. If VPF is less than Vso, the device power is switched from VCC to the backup supply (VBAT) when VCC drops below VPF. If VPF is greater than Vso, the device power is switched from VCC to the backup supply (VBAT) when VCC drops below Vso. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. The RST signal is an open drain output and requires a pull up. Except for the RST , all control, data, and address signals must be powered down when VCC is powered down. BATTERY LONGEVITY The DS1742 has a lithium power source that is designed to provide energy for clock activity, and clock and RAM data retention when the VCC supply is not present. The capability of this internal power supply is sufficient to power the DS1742 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at 25 °C with the internal clock oscillator running in the absence of VCC power. Each DS1742 is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the DS1742 will be much longer than 10 years since no lithium battery energy is consumed when VCC is present. BATTERY MONITOR The DS1742 constantly monitors the battery voltage of the internal battery. The Battery Flag bit (bit 7) of the day register is used to indicate the voltage level range of the battery. This bit is not writable and should always be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated and both the contents of the RTC and RAM are questionable. |
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Similar Description - DS1742-100 |
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