24C04A, 24C08A, 24C16A

Figure 8: SCL and SDA Bus Timing

AC CHARACTERISTICS

1.8 V

2.5-5.0 V

Symbol

Parameter

Min

Max

Min

Max

Unit

Clock frequency, SCL

400

1000

kHz

Clock pulse width low

1.3

0.4

µs

Clock pulse width high

0.6

0.4

µs

180

120

ns

Clock low to data out valid

0.3

0.9

0.2

0.55

µs

Time the bus must be free before a

1.3

0.5

µs

START hold time

0.6

0.25

µs

START set-up time

0.6

0.25

µs

Data in hold time

0

0

µs

Data in set-up time

100

100

ns

0.3

0.3

µs

300

100

ns

STOP set-up time

0.6

0.25

µs

Date out hold time

50

50

ns

WR

Write cycle time

5

5

ms

1,000,000

Write Cycles

Notes: 1. This Parameter is expected by characterization but are not fully screened by test.

2. AC Measurement conditions:

Input Pulse Voltages: 0.3Vcc to 0.7Vcc

Input and output timing reference Voltages: 0.5Vcc

DS3001M-page8

© 2009 Fremont Micro Devices Inc.