DS1350W

022598 2/11

READ MODE

The DS1350W executes a read cycle whenever WE

(Write Enable) is inactive (high) and CE (Chip Enable)

and OE (Output Enable) are active (low). The unique

defines which of the 524,288 bytes of data is to be

accessed. Valid data will be available to the eight data

address input signal is stable, providing that CE and OE

(Output Enable) access times are also satisfied. If OE

and CE access times are not satisfied, then data access

must be measured from the later occurring signal (CE or

for OE rather than address access.

WRITE MODE

The DS1350W excutes a write cycle whenever the WE

and CE signals are in the active (low) state after address

inputs are stable. The later occurring falling edge of CE

or WE will determine the start of the write cycle. The

write cycle is terminated by the earlier rising edge of CE

or WE. All address inputs must be kept valid throughout

the write cycle. WE must return to the high state for a

be initiated. The OE control signal should be kept inac-

tive (high) during write cycles to avoid bus contention.

However, if the output drivers are enabled (CE and OE

falling edge.

DATA RETENTION MODE

greater than 3.0 volts and write protects by 2.8 volts.

additional support circuitry. The nonvolatile static RAMs

decay, the NV SRAMs automatically write protect them-

selves, all inputs become “don’t care,” and all outputs

mately 2.5 volts, the power switching circuit connects

the lithium energy source to RAM to retain data. During

2.5 volts, the power switching circuit connects external

exceeds 3.0 volts.

SYSTEM POWER MONITORING

The DS1350W has the ability to monitor the external

supply condition is detected, the NV SRAM warns a pro-

cessor–based system of impending power failure by

asserting RST. On power up, RST is held active for 200

ms nominal to prevent system operation during pow-

an open–drain output driver.

BATTERY MONITORING

The DS1350W automatically performs periodic battery

voltage monitoring on a 24 hour time interval. Such

and is suspended when power failure occurs.

After each 24 hour period has elapsed, the battery is

connected to an internal 1M

Ω test resistor for one

second. During this one second, if battery voltage falls

below the battery voltage trip point (2.6V), the battery

warning output BW is asserted. Once asserted, BW

remains active until the module is replaced. The battery

if BW is active. If the battery voltage is found to be higher

than 2.6V during such testing, BW is de–asserted and

regular 24–hour testing resumes. BW has an open–

drain output driver.

FRESHNESS SEAL

Each DS1350W is shipped from Dallas Semiconductor

with its lithium energy source disconnected, guarantee-

enabled for battery backup operation.

PACKAGES

The 34–pin PowerCap Module integrates SRAM

memory and nonvolatile control into a module base

along with contacts for connection to the lithium battery

in the DS9034PC PowerCap. The PowerCap Module

package design allows a DS1350W device to be sur-

face mounted without subjecting its lithium backup bat-

tery to destructive high–temperature reflow soldering.

After a DS1350W module base is reflow soldered, a

DS9034PC is snapped on top of the base to form a com-

plete Nonvolatile SRAM module. The DS9034PC is

keyed to prevent improper attachment. DS1350W mod-

ule bases and DS9034PC PowerCaps are ordered sep-

arately and shipped in separate containers. See the

DS9034PC data sheet for further information.