ISL6615A

8

FN6608.2

April 13, 2012

upper and lower MOSFETs, respectively; PVCC is the drive voltage

quiescent power of the driver without capacitive load and is

typically 200mW at 300kHz and VCC = PVCC = 12V.

The total gate drive power losses are dissipated among the

resistive components along the transition path. The drive

resistance dissipates a portion of the total gate drive power

losses; the rest will be dissipated by the external gate resistors

MOSFETs. Figures 3 and 4 show the typical upper and lower gate

drives turn-on transition path. The power dissipation on the driver

can be roughly estimated, as shown in Equation 4.

Application Information

Layout Considerations

The parasitic inductances of the PCB and of the power devices’

packaging (both upper and lower MOSFETs) can cause serious

ringing, exceeding the absolute maximum ratings of the devices.

A good layout helps reduce the ringing on the switching node

(PHASE) and significantly lowers the stress applied to the output

drives. The following advice is meant to lead to an optimized

layout and performance:

• Keep decoupling loops (VCC-GND, PVCC-GND and BOOT-PHASE)

short and wide (at least 25 mils). Avoid using vias on decoupling

components other than their ground terminals, which should be

on a copper plane with at least two vias.

• Minimize trace inductance, especially on low-impedance lines.

All power traces (UGATE, PHASE, LGATE, GND, PVCC, VCC,

GND) should be short and wide (at least 25 mils). Try to place

power traces on a single layer, otherwise, two vias on

interconnection are preferred where possible. For no

connection (NC) pins on the QFN part, connecting them to the

adjacent net (LGATE2/PHASE2) can reduce trace inductance.

• Shorten all gate drive loops (UGATE-PHASE and LGATE-GND)

and route them closely spaced.

• Minimize the inductance of the PHASE node. Ideally, the

source of the upper and the drain of the lower MOSFET should

be as close as thermally allowable.

• Minimize the current loop of the output and input power trains.

Short the source connection of the lower MOSFET to ground as

close to the transistor pin as feasible. Input capacitors

(especially ceramic decoupling) should be placed as close to

the drain of upper and source of lower MOSFETs as possible.

• Avoid routing relatively high impedance nodes (such as PWM

and ENABLE lines) close to high dV/dt UGATE and PHASE

nodes.

In addition, for heat spreading, place copper underneath the IC

whether it has an exposed pad or not. The copper area can be

extended beyond the bottom area of the IC and/or connected to

buried power ground plane(s) with thermal vias. This

combination of vias for vertical heat escape, extended copper

plane, and buried planes for heat spreading allows the IC to

achieve its full thermal potential.

Upper MOSFET Self Turn-On Effects at

Start-up

Should the driver have insufficient bias voltage applied, its

outputs are floating. If the input bus is energized at a high dV/dt

rate while the driver outputs are floating due to the self-coupling

momentarily rise up to a level greater than the threshold voltage

of the MOSFET. This could potentially turn on the upper switch

and result in damaging inrush energy. Therefore, if such a

situation (when input bus powered up before the bias of the

controller and driver is ready) could conceivably be encountered,

gate and source of the upper MOSFET to suppress the Miller

coupling effect. The value of the resistor depends mainly on the

FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

•

++

=

(EQ. 4)

+

-----------------------------------

+

-------------------------------------

+

⎝⎠

⎜⎟

2

-------------------

•

=

+

-----------------------------------

+

-------------------------------------

+

⎝⎠

⎜⎟

2

-------------------

•

=

------------

+

=

------------

+

=

Q1

D

S

G

BOOT

PHASE

PVCC

PVCC

Q2

D

S

G