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DS1220 Datasheet(PDF) 7 Page - Dallas Semiconductor |
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DS1220 Datasheet(HTML) 7 Page - Dallas Semiconductor |
7 / 9 page DS1220AB/AD 7 of 9 POWER-DOWN/POWER-UP CONDITION SEE NOTE 11 POWER-DOWN/POWER-UP TIMING (tA: See Note 10) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES CE at VIH before Power-Down tPD 0 µs 11 VCC slew from VTP to 0v tF 300 µs VCC slew from 0V to VTP tR 300 µs CE at VIH after Power-Up tREC 2 125 ms (TA =25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Expected Data Retention Time tDR 10 years 9 WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in the battery backup mode. NOTES: 1. WE is high for a read cycle. 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state. 3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or CE going low to the earlier of CE or WE going high. 4. tDS is measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 5 pF load and are not 100% tested. 6. If the CE low transition occurs simultaneously with or later than the WE low transition, the output buffers remain in a high-impedance state during this period. |
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