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CY7C056V
CY7C057V
8
PRELIMINARY
Switching Characteristics Over the Operating Range[13]
Parameter
Description
CY7C056V
CY7C057V
Unit
-10
-12
-15
-20
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
tRC
Read Cycle Time
10
12
15
20
ns
tAA
Address to Data Valid
10
12
15
20
ns
tOHA
Output Hold From Address
Change
33
3
3
ns
tACE
[3, 14]
CE LOW to Data Valid
10
12
15
20
ns
tDOE
OE LOW to Data Valid
6
8
10
12
ns
tLZOE
[3, 15, 16, 17]
OE Low to Low Z
0
0
0
0
ns
tHZOE
[3, 15, 16, 17]
OE HIGH to High Z
8
10
10
12
ns
tLZCE
[3, 13, 16, 17]
CE LOW to Low Z
3
3
3
3
ns
tHZCE
[3, 15, 16, 17]
CE HIGH to High Z
8
10
10
12
ns
tLZBE
Byte Enable to Low Z
3
3
3
3
ns
tHZBE
Byte Enable to High Z
8
10
10
12
ns
tPU
[3, 17]
CE LOW to Power-Up
0
0
0
0
ns
tPD
[3, 17]
CE HIGH to Power-Down
10
12
15
20
ns
tABE
[14]
Byte Enable Access Time
10
12
15
20
ns
Write Cycle
tWC
Write Cycle Time
10
12
15
20
ns
tSCE
[3, 14]
CE LOW to Write End
7.5
10
12
15
ns
tAW
Address Valid to Write End
7.5
10
12
15
ns
tHA
Address Hold From Write
End
00
0
0
ns
tSA
[14]
Address Set-Up to Write
Start
00
0
0
ns
tPWE
Write Pulse Width
7.5
10
12
15
ns
tSD
Data Set-Up to Write End
7.5
10
10
15
ns
tHD
Data Hold From Write End
0
0
0
0
ns
tHZWE
[16, 17]
R/W LOW to High Z
8
10
10
12
ns
tLZWE
[16, 17]
R/W HIGH to Low Z
3
3
3
3
ns
tWDD
[18]
Write Pulse to Data Delay
20
25
30
45
ns
tDDD
[18]
Write Data Valid to Read
Data Valid
16
20
25
30
ns
Busy Timing[19]
tBLA
BUSY LOW from Address
Match
10
12
15
20
ns
tBHA
BUSY HIGH from Address
Mismatch
10
12
15
20
ns
tBLC
BUSY LOW from CE LOW
10
12
15
20
ns
Notes:
13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOI/IOH and 10-pF load capacitance.
14. To access RAM, CE = L and SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
15. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
16. Test conditions used are Load 2.
17. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading
port, refer to Read Timing with Busy waveform.
18. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
19. Test conditions used are Load 1.
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