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IS42S16400J-6BLI Datasheet(PDF) 6 Page - List of Unclassifed Manufacturers

Part # IS42S16400J-6BLI
Description  1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
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IS42S16400J-6BLI Datasheet(HTML) 6 Page - List of Unclassifed Manufacturers

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Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
12/17/2013
IS42S16400J
IS45S16400J
PIN FUNCTIONS
Symbol
TSOP Pin No.
Type
Function
A0-A11
23 to 26
Input Pin
AddressInputs:A0-A11aresampledduringtheACTIVE
29to34
command(row-addressA0-A11)andREAD/WRITEcommand(A0-A7
22, 35
with A10 defining auto precharge) to select one location out of the memory array
intherespectivebank.A10issampledduringaPRECHARGEcommandtodeter-
mineifallbanksaretobeprecharged(A10HIGH)orbankselectedby
BA0,BA1(LOW).Theaddressinputsalsoprovidetheop-codeduringaLOAD
MODEREGISTERcommand.
BA0,BA1
20, 21
Input Pin
BankSelectAddress:BA0andBA1defineswhichbanktheACTIVE,READ,WRITE
orPRECHARGEcommandisbeingapplied.
CAS
17
Input Pin
CAS
, in conjunction with the RAS and WE, forms the device command. See the
"CommandTruthTable"fordetailsondevicecommands.
CKE
37
Input Pin
TheCKEinputdetermineswhethertheCLKinputisenabled.Thenextrisingedge
oftheCLKsignalwillbevalidwhenisCKEHIGHandinvalidwhenLOW.WhenCKE
isLOW,thedevicewillbeineitherpower-downmode,clocksuspendmode,orself
refresh mode. CKEisan asynchronous input.
CLK
38
Input Pin
CLKisthemasterclockinputforthisdevice.ExceptforCKE,allinputstothisdevice
are acquired in synchronization with the rising edge of this pin.
CS
19
InputPin
TheCS input determines whether command input is enabled within the device.
Command input is enabled when CSisLOW,anddisabledwithCSisHIGH.The
device remains in the previous state when CSisHIGH.
DQ0 to
2, 4, 5, 7, 8, 10,
DQ Pin
DQ0toDQ15areI/Opins.I/Othroughthesepinscanbecontrolledinbyteunits
DQ15
11,13, 42, 44, 45,
usingtheLDQMandUDQMpins.
47, 48, 50, 51, 53
LDQM,
15,39
InputPin
LDQMandUDQMcontrolthelowerandupperbytesoftheI/Obuffers.Inread
UDQM
mode,LDQMandUDQMcontroltheoutputbuffer.WhenLDQMorUDQMisLOW,
thecorrespondingbufferbyteisenabled,andwhenHIGH,disabled.Theoutputs
gototheHIGHimpedancestatewhenLDQM/UDQMisHIGH.Thisfunctioncor-
responds to OEinconventionalDRAMs.Inwritemode,LDQMandUDQMcontrol
theinputbuffer.WhenLDQMorUDQMisLOW,thecorrespondingbufferbyteisen-
abled,anddatacanbewrittentothedevice.WhenLDQMorUDQMisHIGH,input
data is masked and cannot be written to the device.
RAS
18
Input Pin
RAS
, in conjunction with CAS and WE, forms the device command. See the "Com-
mandTruthTable"itemfordetailsondevicecommands.
WE
16
Input Pin
WE
, in conjunction with RAS and CAS, forms the device command. See the "Com-
mandTruthTable"itemfordetailsondevicecommands.
Vddq
3,9,43,49
PowerSupplyPinVddq is the output buffer power supply.
Vdd
1, 14, 27
Power Supply PinVdd is the device internal power supply.
GNdq
6, 12, 46, 52
Power Supply PinGNdq is the output buffer ground.
GNd
28, 41, 54
Power Supply PinGNd is the device internal ground.


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