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CS5317-KP Datasheet(PDF) 5 Page - Cirrus Logic |
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CS5317-KP Datasheet(HTML) 5 Page - Cirrus Logic |
5 / 32 page 2.0 V 0.8 V t fallin t risein 2.4 V 0.4 V triseout t fallout Rise and Fall Times DATA CLKOUT (Note 15) CLKIN DOUT DOE CLKIN t pwh1 t pwl1 CLKIN CLKOUT (Note 14) t plh5 t su1 t su2 t pwr t plh5 t su1 t su2 t plh6 RST DOUT t plh1 t plh2 t plh3 t phl2 t phl1 14 10 15 (MSB) (Note 16) t plh4 Notes: 14. CLKIN only pertains to CLKG1 and CLKG2 modes. 15. If DOE is brought high during serial data transfer, CLKOUT, DOUT, and DATA will immediately 3-state and the rest of the serial data is lost. 16. RST must be held high except in the clock override (CLKOR) mode where it can be used to align the phases of all internal clocks. CLKIN Timing Serial Output Timing Reset Timing CS5317 DS27F4 5 |
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