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CS4299-BQ Datasheet(PDF) 7 Page - Cirrus Logic |
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CS4299-BQ Datasheet(HTML) 7 Page - Cirrus Logic |
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7 / 52 page  CS4299-BQ 7 AC ’97 SERIAL PORT TIMING Standard test conditions unless otherwise noted: T ambient = 25° C, AVdd = 5.0 V, DVdd = 3.3 V; CL = 55 pF load. Parameter Symbol Min Typ Max Unit RESET Timing RESET# active low pulse width Trst_low 1.0 - - µs RESET# inactive to BIT_CLK start-up delay Trst2clk - 40.0 - µs 1st SYNC active to CODEC READY set Tsync2crd - 62.5 - µs Vdd stable to Reset inactive Tvdd2rst# 100 - - µs Clocks BIT_CLK frequency Fclk - 12.288 - MHz BIT_CLK period Tclk_period - 81.4 - ns BIT_CLK output jitter (depends on XTAL_IN source) - - 750 ps BIT_CLK high pulse width Tclk_high 36 40.7 45 ns BIT_CLK low pulse width Tclk_low 36 40.7 45 ns SYNC frequency Fsync - 48 - kHz SYNC period Tsync_period - 20.8 - µs SYNC high pulse width Tsync_high - 1.3 - µs SYNC low pulse width Tsync_low - 19.5 - µs Data Setup and Hold Output Propagation delay from rising edge of BIT_CLK Tco - 12 - ns Input setup time from falling edge of BIT_CLK Tisetup 10 - - ns Input hold time from falling edge of BIT_CLK Tihold 0 - - ns Input Signal rise time Tirise 2 - 6 ns Input Signal fall time Tifall 2 - 6 ns Output Signal rise time (Note 4) Torise 2 4 6 ns Output Signal fall time (Note 4) Tofall 2 4 6 ns Misc. Timing Parameters End of Slot 2 to BIT_CLK, SDATA_IN low (PR4) Ts2_pdown - .28 1.0 µs SYNC pulse width (PR4) Warm Reset Tsync_pr4 1.0 - - µs SYNC inactive (PR4) to BIT_CLK start-up delay Tsync2clk 162.8 285 - ns Setup to trailing edge of RESET# (ATE test mode) (Note 4) Tsetup2rst 15 - - ns Rising edge of RESET# to Hi-Z delay (Note 4) Toff - - 25 ns |
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