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EP4CGX150 Datasheet(PDF) 11 Page - Altera Corporation |
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EP4CGX150 Datasheet(HTML) 11 Page - Altera Corporation |
11 / 14 page Chapter 1: Cyclone IV FPGA Device Family Overview 1–11 Cyclone IV Device Family Architecture February 2013 Altera Corporation Cyclone IV Device Handbook, Volume 1 Figure 1–1 shows the structure of the Cyclone IV GX transceiver. f For more information, refer to the Cyclone IV Transceivers Architecture chapter. Hard IP for PCI Express (Cyclone IV GX Devices Only) Cyclone IV GX devices incorporate a single hard IP block for ×1, ×2, or ×4 PCIe (PIPE) in each device. This hard IP block is a complete PCIe (PIPE) protocol solution that implements the PHY-MAC layer, Data Link Layer, and Transaction Layer functionality. The hard IP for the PCIe (PIPE) block supports root-port and end-point configurations. This pre-verified hard IP block reduces risk, design time, timing closure, and verification. You can configure the block with the Quartus II software’s PCI Express Compiler, which guides you through the process step by step. f For more information, refer to the PCI Express Compiler User Guide. Figure 1–1. Transceiver Channel for the Cyclone IV GX Device TX Phase Compensation FIFO Byte Serializer 8B10B Encoder Receiver Channel PCS Receiver Channel PMA Transmitter Channel PCS Transceiver Channel PMA FPGA Fabric |
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