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U74HCT7046L-S16-T Datasheet(PDF) 11 Page - Unisonic Technologies |
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U74HCT7046L-S16-T Datasheet(HTML) 11 Page - Unisonic Technologies |
11 / 16 page U74HCT7046 CMOS IC UNISONICTECHNOLOGIESCO.,LTD 11 of 16 www.unisonic.com.tw QW-R502-851.A PHASE COMPARATORS (Cont.) If the frequencies of SIGIN and COMPIN are equal but the phase of SIGIN leads that of COMPIN, the p-type output driver at PC2OUT is held “ON” for a time corresponding to the phase difference (φDEMOUT). If the phase of SIGIN lags that of COMPIN, the n-type driver is held “ON”. If the frequency of SIGIN is higher than that of COMPIN, the p-type output driver is held “ON” for most of the input signal cycle time, and for the remainder of the cycle both n and p-type drivers are “OFF” (3-state). If the frequency of SIGIN is lower than that of COMPIN, the n-type driver that is held “ON” for most of the cycle. Then the voltage at the capacitor (C2) of the low-pass filter connected to PC2OUT varies until the signal and comparator inputs are equal in both phase and frequency. At this stable state the voltage on C2 remains constant as the PC2 output is in 3-state and the VCO input at pin 9 is a high impedance. Also in the condition, the signal at the phase comparator pulse output (PCPOUT) is a HIGH level, and it indicates a locked condition. For PC2, there is no phase difference between SIGIN and COMPIN over the full frequency range of the VCO. And as the low-pass filter, the power dissipation is reduced because both p and n-type drivers are “OFF” for most of the signal input cycle. It should be noted that the PLL lock range for this type of phase comparator is equal to the capture range and this is independent of the low-pass filter. The VCO adjusts to its lowest frequency via PC2 when no signal present at SIGIN. LOCK DETECTOR THEORY OF OPERATION Detection of a locked condition is accomplished by a NOR gate and an envelope detector.When the PLL is in Lock, the output of the NOR gate is High and the lock detector output (Pin 1) is at a constant high level. As the loop tracks the signal on Pin 14 (signal in), the NOR gate outputs pulses whose widths represent the phase differ-ences between the VCO and the input signal. The time between pulses will be approximately equal to the time constant of the VCO center frequency. During the rise time of the pulse, the diode across the 1.5kΩ resistor is forward biased and the time constant in the path that charges the lock detector capacitor is T = (150Ω x CLD). During the fall time of the pulse the capacitor discharges through the 1.5kΩ and the 150Ω resistors and the channel resistance of the n-device of the NOR gate to ground (T = (1.5kΩ + 150Ω + Rn-channel) x CLD). The waveform preset at the capacitor resembles a sawtooth.The lock detector capacitor value is determined by the VCO center frequency. The typical range of capacitor for a frequency of 10MHz is about 10pF and for a frequency of 100kHz is about 1000pF. As long as the loop remains locked and tracking, the level of the sawtooth will not go below the switching threshold of the Schmitt-trigger inverter. If the loop breaks lock, the width of the error pulse will be wide enough to allow the sawtooth waveform to go below threshold and a level change at the output of the Schmitt trigger will indicate a loss of lock. The lock detector capacitor also acts to filter out small glitches that can occur when the loop is either seeking or losing lock. FIGURE REFERENCES FOR DC CHARACTERISTICS Self-Bias Operating Point VIN IIN VIN Fig.7 Typical input resistance curve at SIGIN, COMPIN. |
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