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SLN08G72G2BE2MT-DCRT Datasheet(PDF) 8 Page - List of Unclassifed Manufacturers |
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SLN08G72G2BE2MT-DCRT Datasheet(HTML) 8 Page - List of Unclassifed Manufacturers |
8 / 17 page preliminary Data Sheet Rev.0.9 14.12.2012 Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 8 CH – 9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 17 Parameter & Test Condition Symbol max. Unit 12800 CL11 10600 CL9 OPERATING WRITE CURRENT: All device banks open, Continuous burst writes; One module rank active; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle IDD4W 945 810 mA BURST REFRESH CURRENT: tCK = tCK (IDD); refresh command at every tRFC (IDD) interval, CKE is HIGH, CS# is HIGH between valid commands; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle IDD5 2610 2160 mA SELF REFRESH CURRENT: CK and CK# at 0V; CKE ≤ 0.2V; All other Control and Address bus inputs are floating at VREF; DQ’s are floating at VREF IDD6 270 270 mA OPERATING CURRENT*) : Four device bank interleaving READs, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) – 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are not changing during DESELECT; DQ inputs changing once per clock cycle IDD7 1665 1305 mA *) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode. TIMING VALUES USED FOR IDD MEASUREMENT IDD MEASUREMENT CONDITIONS SYMBOL 128000 CL11 10600 CL9 Unit CL (IDD) 11 9 tCK tRCD (IDD) 13.75 13.5 ns tRC (IDD) 48.75 49.5 ns tRRD (IDD) 5 6 ns tCK (IDD) 1.25 1.5 ns tRAS MIN (IDD) 35 36 ns tRAS MAX (IDD) 70 ’200 70’200 ns tRP (IDD) 13.75 13.5 ns tRFC (IDD) 260 260 ns |
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