SLN04G72G2BF2HY-DCRT datasheet(1/17 Pages) ETC2

Part #	SLN04G72G2BF2HY-DCRT

Description	4096MB DDR3L ??SDRAM ECC SO-DIMM

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preliminary

Data Sheet

Rev.0.9

26.07.2013

Swissbit AG

Industriestrasse 4

Fon: +41 (0) 71 913 03 03

www.swissbit.com

Page 1

CH

– 9552 Bronschhofen

Fax: +41 (0) 71 913 03 15

eMail: info@swissbit.com

of 17

Figure: mechanical dimensions

1

4096MB DDR3L – SDRAM ECC SO-DIMM

204 Pin ECC SO-UDIMM

SLN04G72G2BF2HY-xxRT

4GByte in FBGA Technology

RoHS compliant

*) The refresh rate has to be doubled when 85°C<TC<95°C

Environmental Requirements:



Operating temperature (ambient)

Standard Grade

0°C to 70°C



Operating Humidity

10% to 90% relative humidity, noncondensing



Operating Pressure

105 to 69 kPa (up to 10000 ft.)



Storage Temperature

-55°C to 100°C



Storage Humidity

5% to 95% relative humidity, noncondensing



Storage Pressure

1682 PSI (up to 5000 ft.) at 50°C

Options:



Data Rate / Latency

Marking

DDR3 1333 MT/s CL9

-CC

DDR3 1600 MT/s CL11

-DC



Module density

4096MB with 18 dies and 2 ranks

 Standard Grade

(TA)

0°C to 70°C

(TC)

0°C to 85°C

Features:



204-pin 72-bit DDR3 Small Outline, Dual-In-Line Double

Data Rate synchronous DRAM Module



Module organization: dual rank 512M x 72



VDD = 1.35V and 1.5V



VDDQ = 1.35V and 1.5V



SSTL_15 compatible



Fly-by-bus with termination for C/A & CLK bus



On-board I

2C temperature sensor with integrated serial

presence-detect (SPD) EEPROM



Gold-contact pad



This module is fully pin and functional compatible to the

JEDEC EP3-12800 DDR3 SDRAM 72bit-SO-DIMM

design spec. and JEDEC- Standard MO-268. (see

www.jedec.org)



The pcb and all components are manufactured according

to the RoHS compliance specification

[EU Directive 2002/95/EC Restriction of Hazardous

Substances (RoHS)]



DDR3 - SDRAM component Hynix

H5TC2G83FFR-PBA



256Mx8 DDR3 SDRAM in PG-TFBGA-78 package



8-bit prefetch architecture



Programmable CAS Latency, CAS Write Latency, Additive

Latency, Burst Length and Burst Type.



On-Die-Termination (ODT) and Dynamic ODT for

improved signal integrity.



Refresh, Self Refresh and Power Down Modes.



ZQ Calibration for output driver and ODT.



System Level Timing Calibration Support via Write

Leveling and Multi Purpose Register (MPR) Read Pattern.

1

if no tolerances specified ± 0.15mm

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