preliminary

Data Sheet

Rev.0.9

26.07.2013

Swissbit AG

Industriestrasse 4

Fon: +41 (0) 71 913 03 03

www.swissbit.com

Page 2

CH

– 9552 Bronschhofen

Fax: +41 (0) 71 913 03 15

eMail: info@swissbit.com

of 17

This Swissbit module is an industry standard 204-pin 8-byte DDR3 SDRAM ECC Small Outline Dual-In-line

Memory Module (SO-UDIMM) which is organized as x72 high speed CMOS memory arrays. The module uses

internally configured octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to

achieve high-speed operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ

and WRITE accesses to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and

continue for a programmed number of locations in a programmed sequence. The burst length is either four or

eight locations. An auto precharge function can be enabled to provide a self-timed row precharge that is initiated

at the end of a burst access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent

operation that is providing a high effective bandwidth. A self refresh mode is provided and a power-

saving “power-

down” mode. All inputs and all full drive-strength outputs are SSTL_15 compatible.

The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM

using the standard I

utilized by the SO-U

DIMM manufacturer (Swissbit) to identify the module type, the module’s organization and

several timing parameters. The second 128 bytes are available to the end user.

Module Configuration

Organization

DDR3 SDRAMs used

Row

Addr.

Device Bank

Addr.

Column

Addr.

Refresh

Module

Bank Select

512M x 72bit

18 x 256M x 8bit (2Gbit)

15

BA0, BA1, BA2

10

8k

S0#, S1#

Module Dimensions

in mm

67.60 (long) x 30(high) x 3.80 [max] (thickness)

Timing Parameters

Part Number

Module Density

Transfer Rate

Clock Cycle/Data bit rate

Latency

SLN04G72G2BF2HY-CCRT

4GByte

10.6 GB/s

1.5ns/1333MT/s

9-9-9

SLN04G72G2BF2HY-DCRT

4GByte

12.8 GB/s

1.25ns/1600MT/s

11-11-11

Pin Name

A0

– A9, A11 – A14

Address Inputs

A10/AP

Address Input / Autoprecharge Bit

BA0

– BA2

Bank Address Inputs

DQ0

– DQ63

Data Input / Output

CB0

– CB07

ECC check bits

DM0

– DM8

Input Data Mask

DQS0

– DQS8

Data Strobe, positive line

DQS0#

– DQS8#

Data Strobe, negative line (only used when differential data strobe mode is enabled)

RAS#

Row Address Strobe

CAS#

Column Address Strobe

WE#

Write Enable

CKE0

– CKE1

Clock Enable

S0#, S1#

Chip Select

CK0

– CK1

Clock Inputs, positive line

CK0#

– CK1#

Clock Inputs, negative line

Figure 1: Mechanical Dimensions