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SLN02G72F1BK1MT-CCRT Datasheet(PDF) 9 Page - List of Unclassifed Manufacturers |
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SLN02G72F1BK1MT-CCRT Datasheet(HTML) 9 Page - List of Unclassifed Manufacturers |
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9 / 17 page  Data Sheet Rev.1.0 24.05.2013 Swissbit AG Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 9 CH – 9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 17 DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (0°C ≤ TCASE ≤ + 85°C; VDDQ, VDD = +1.283V – 1.45V) AC CHARACTERISTICS 12800-CL11 10600-CL9 PARAMETER SYMBOL MIN MAX MIN MAX Unit Clock cycle time CL = 11 tCK (11) 1.25 - - - ns CL = 10 tCK (10) 1.5 <1.875 1.5 <1.875 CL = 9 tCK (9) 1.5 <1.875 1.5 <1.875 CL = 8 tCK (8) 1.875 <2.5 1.875 <2.5 CL = 7 tCK (7) 1.875 <2.5 1.875 <2.5 CL = 6 tCK (6) 2.5 3.3 2.5 3.3 CL = 5 tCK (5) 3.0 3.3 3.0 3.3 Internal READ command to first data tAA 13.75 - 13.5 - CK high-level width tCH (avg) 0.47 0.53 0.47 0.53 tCK CK low-level width tCL (avg) 0.47 0.53 0.47 0.53 tCK Data-out high-impedance window from CK/CK# tHZ - 225 - 250 ps Data-out low-impedance window from CK/CK# tLZ -450 225 -500 250 ps DQ and DM input setup time relative to DQS VREF=1V/ns tDS1V 160 - 180 - ps DQ and DM input hold time relative to DQS VREF=1V/ns tDH1V 145 - 165 - ps DQ and DM input pulse width ( for each input ) tDIPW 360 - 400 - ps DQS, DQS# to DQ skew, per access tDQSQ - 100 - 125 ps DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH 0.38 - 0.38 - tCK (AVG) DQS input high pulse width tDQSH 0.45 0.55 0.45 0.55 tCK DQS input low pulse width tDQSL 0.45 0.55 0.45 0.55 tCK DQS, DQS# rising to/from CK, CK# tDQSCK -225 225 -250 250 ps DQS, DQS# rising to/from CK, CK# when DLL disabled tDQSCK DLL_DIS 1 10 1 10 ns DQS falling edge to CK rising - setup time tDSS 0.18 - 0.2 - tCK DQS falling edge from CK rising - hold time tDSH 0.18 - 0.2 - tCK DQS read preamble tRPRE 0.9 Note 1 0.9 Note 1 tCK DQS read postamble tRPST 0.3 Note 2 0.3 Note 2 tCK DQS write preamble tWPRE 0.9 - 0.9 - tCK DQS write postamble tWPST 0.3 - 0.3 - tCK Positive DQS latching edge to associated clock edge tDQSS - 0.27 + 0.27 - 0.25 + 0.25 tCK Address and control input pulse width ( for each input ) tIPW 560 - 620 - ps CTRL, CMD, Addr setup to CK, CK# tIS(Base) 45 - 65 - ps CTRL, CMD, Addr setup to CK, CK# VREF @ 1V/ns tIS(1V) 220 - 240 - ps 1 The maximum preamble is bound by tLZDQS (MAX) 2 The maximum postamble is bound by tHZDQS (MAX) |
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